Data Sheet S10299EJ4V0DS00

7

Table 1–1. Processing CA1, CA0 Pins

Mode

CA1, CA0

With chip address function

- Always in parallel mode

- When CAE = 1 in serial mode

Set to 00, 01, 10, or 11

(always 00 in single chip configuration)

Without chip address function

- When CAE = 0 in serial mode

Always set to 00

Remark In a multi-chip configuration in the serial interface mode, chip selection is also

possible by providing decoded /CS signals for the number of chips used, without

using the chip address function. In this case, CAE for each chip must be set to 0,

and CA1 and CA0 pins must be set to 00.

These are Schmitt trigger inputs with hysteresis in order to prevent erroneous operation caused by noise.

1.7 /CS (Chip Select) … Input

This is the chip select input, which is low active.

When the chip address function is not used, if a low is input to the /CS input, the /STB, /SCK and C, /D inputs

become effective, so that commands and data can be input/output.

When the chip address function is used, in order for the /STB, /SCK and C, /D inputs to become effective, the chip

address information and CA0 and CA1 inputs must coincide, and moreover, the /CS input should become low.

When the /CS input is set to high, D3-D0 and /BUSY pins unconditionally become high impedance.

This is a Schmitt trigger input with hysteresis in order to prevent erroneous operation caused by noise.

1.8 /STB, /SCK (Strobe/Serial Clock) … Input

In the parallel interface mode, this pin serves as the strobe signal input pin (STB) for 4-bit parallel data

input/output operation. In the serial interface mode, this pin serves as the serial clock input pin (/SCK) for serial data

input/output operation.

1.9 C, /D (Command/Data) … Input

This pin is used to identify whether serial or parallel data input is a command or data. When inputting a command,

set the C, /D pin to high. When inputting data, set to low.

When inputting a command or data in the parallel interface mode, the command or data is latched at the second

/STB rising edge. In the serial interface mode, the command or data is latched at the rising edge of the 8th /SCK.

However, in parallel input, switching C, /D must be performed, before the falling edge of the 1st /STB.

When outputting data, C, /D input must always be set to low, regardless of whether the mode is parallel or serial.

This is a Schmitt trigger input with hysteresis in order to prevent erroneous operation caused by noise.

1.10 /BUSY (Busy) … 3-state output

This pin outputs a /BUSY signal which indicates to the CPU that the

µ PD16434 is busy because of internal

processing.

If this signal is low,

µ PD16434 is busy, and the CPU cannot execute read/write to the µ PD16434.

The /BUSY signal becomes low at second rising of the /STB signal in the parallel interface mode. In the serial

interface mode, the /BUSY signal becomes low at the rising edge of the 8th /SCK.

The

µ PD16434 sets the /BUSY signal to high, when the µ PD16434 completes the internal processing.

The /BUSY output becomes high impedance, when the chip is not selected (/CS = high or the chip address does

not coincide).