Data Sheet S10299EJ4V0DS00

6

1. PIN FUNCTIONS

1.1 D0 to D3 (Data Bus) … 3-state input/output

In the parallel interface mode, these pins serve as 4-bit parallel data input/output pins.

Data on the D0 to D3 lines is read at the /STB signal rising edge. The 4-bit data, read at the first rising edge of the

/STB, is loaded into the upper 4 bits of the serial/parallel register, and the data read at the second rising edge is loaded

into the lower 4 bits of the register.

The serial/parallel register contents are output to the D0 to D3 pins in synchronization with the /STB signal falling

edge. In the same manner as read operation, the upper 4 bits of the serial/parallel register are output in the first /STB

signal falling edge, and the lower 4bits are output in the second /STB falling edge.

In the serial interface mode, the D0 serves as the serial data input pin (SI), and the D3 pin serves as the serial

data output pin (SO).

The D1 pin serves as the parallel/serial interface mode selection pin (P, /S), and the D2 pin serves as the chip

address enable pin (CAE).

1.2 SI (Serial Data In) … Also serves as D0 input

This pin serves as the serial data input pin in the serial interface mode. Data on the SI line is loaded into the

serial/parallel register at the /SCK rising edge. The first data becomes the MSB. This is a Schmitt trigger input with

hysteresis, in order to prevent erroneous operation caused by noise.

1.3 SO (Serial Data Out) … Also serves as D3 output

This pin serves as the serial data output pin in the serial interface mode. The serial/parallel register contents are

output to the SO pin with the MSB first in synchronization with the /SCK pin falling edge.

1.4 P, /S (Parallel/Serial Select) … Also serves as D1 input

This pin is sampled at the RESET signal falling edge (when the reset is released). If this pin is high, the parallel

interface mode is set. If it is low, the serial interface mode is set. This is a Schmitt trigger input with hysteresis in

order to prevent erroneous operation caused by noise.

1.5 CAE (Chip Address Enable) … Also serves as D2 input

The CAE input has a meaning, if P, /S input is low (when the serial interface mode is specified) at the RESET

signal falling edge (when reset is released). If the CAE signal is high at this timing, the chip address function is enabled.

If the CAE signal is low, the chip address function is disabled. This is a Schmitt trigger input with

hysteresis in order to prevent erroneous operation caused by noise.

1.6 CA0, CA1 (Chip Address) … Input

This is the input pin used to allocate the inherent address to select each

µ PD16434 chip, when interfacing with

the CPU in a multi-chip configuration. In the parallel interface mode, CA0 and CA1 inputs are compared with the

chip address information sent from the CPU, regardless of the CAE input. In the serial interface mode, these inputs are

compared with the chip address information sent from the CPU, when the chip address selection function is enabled by

the CAE input.