Data Sheet S10299EJ4V0DS00

19

2.6 LCD Voltage Control Circuit

the AC signal synchronized with the CLOCK and SYNC signal, and supplies the signals to determine the select and

non-select level of the row and column signals and the phase for the row and column drivers.

Table 2–1 indicates these signal levels and the phase.

Table 2–1. LCD Driver Voltage Signal Levels and Phase

8-time-divisions

16-time-divisions

–+–

+

Row

Select

Non-select

Column

Select

Non-select

Note

2.7 LCD Timing Control Circuit

This circuit generates the timing signals from the clock signal, according to the frame frequency specified by the

SFF command, and the number of time divisions specified by the SMM command.

The timing signals are necessary for automatically reading the display data and driving the LCD, and are supplied

to the data memory row/column driver, and LCD voltage control circuit.

If the SYNC signal is set to the output mode by the SMM command, the SYNC signal is output for each frame. If

the SYNC mode is specified to the input mode, the SYNC signal supplied from some other chip is input to generate the

timing signals in synchronization with each frame interval.

The SYNC signal input/output function is used to synchronize the LCD drive timing between chips in multi-chip

configuration.

2.8 Row/Column Driver

The row/column driver consists of the column driver for C0 to C41 signals, row/column driver for R15 to R8 and

C42 to C49, and a dual mode row driver for R0 to R7 or R8 to R15.

The dual mode row driver function is determined by the SMM command.