µPD9903

9

(2) AC conditions

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Units

Data clock frequency

± 50 ppm

2048

kHz

Data clock pulse width

200

ns

Frame sync clock frequency

± 50 ppm

8.0

kHz

High level frame sync pulse

× 8ns

width

Low level frame sync pulse

× 8ns

width

Clock rise time

30

ns

Clock fall time

30

ns

Float in sync timing

100

ns

40

ns

High level width of frame

100

ns

sync clock and data clock

Note 1

65

ns

Note 1

120

ns

Minimum width of reset pulse

10

µs

Notes 1. During timing measurement, use 5 ns as the rise time and fall time for the digital input wave form and

clock signal.

2. The

µPD9903 is initialized when high level input is applied to the RST pin after applying low level input

for several clock widths. (However, use of the RST pin is not guaranteed during low level input. Also,

low level input alone does not initialize the

µPD9903.)