TPS717 datasheet(17/42 Pages) TI

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SOC

PLL

COUT

GND

CIN

OUT

Buck Regulator

TPS71701

3.3 V

2.8 V

100

s/div

50 mV/div

40 mV/div

OUT

= 3.3 V

150 mA

1 mA

= 1

OUT

TPS717

www.ti.com

SBVS068H – FEBRUARY 2006 – REVISED JANUARY 2015

Table 3. Sample 1% Resistor Values for Common

Output Voltages

VOUT

80.6 k

Ω

324 k

Ω

1.2

162 k

Ω

324 k

Ω

1.5

294 k

Ω

332 k

Ω

1.8

402 k

Ω

324 k

Ω

2.5

665 k

Ω

316 k

Ω

3.3

1.02 M

Ω

324 k

Ω

1.74 M

Ω

332 k

Ω

8.2.1.3 Application Curve

Figure 35. Load Transient Response

8.2.2 Powering a PLL Integrated on an SOC

Figure 36 shows the TPS71701 powering a phase-locked loop (PLL) that is integrated into a system-on-a-chip

(SOC).

Figure 36. Typical Application Circuit: PLL on an SOC

Use the input and output capacitors to ensure the voltage transient requirements. A 1-µF input and 1-µF output

capacitor are selected to maximize the capacitance and minimize capacitor size.

R2 is chosen to be 158 kΩ for optimal noise and PSRR, and by Equation 4, R1 is selected to be 402 kΩ. Both R1

and R2 must be 1% tolerance resistors to meet the dc accuracy specification over line, load, and temperature.

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