TPS717 datasheet(20/42 Pages) TI

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:T =T +

OUT

Thermal Pad

CIN

COUT

(1)

TPS717

SBVS068H – FEBRUARY 2006 – REVISED JANUARY 2015

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Layout Example (continued)

(1)

Circles within thermal pad area indicate vias to other layers on the board, for electrical connections or thermal

conduction.

Figure 38. Adjustable Voltage Layout

10.3 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in

the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves

the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in

Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The

addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of

the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 4:

(4)

A better method of estimating the thermal measure comes from using the thermal metrics

ΨJT and ΨJB, shown in

Thermal Information. These metrics are a more accurate representation of the heat transfer characteristics of the

die and the package than RθJA. The junction temperature can be estimated with Equation 5.

where

•

PD is the power dissipation shown by Equation 4,

•

TT is the temperature at the center-top of the IC package,

•

TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface.

(5)

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