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TPS717 Datasheet(PDF) 19 Page - Texas Instruments

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Part # TPS717
Description  TPS717xx Low-Noise, High-Bandwidth PSRR,Low-Dropout, 150-mA Linear Regulator
PDF  42 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS717 Datasheet(HTML) 19 Page - Texas Instruments

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Thermal Pad
CIN
COUT
CNR
(1)
TPS717
www.ti.com
SBVS068H – FEBRUARY 2006 – REVISED JANUARY 2015
10 Layout
10.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close to the GND pin as possible, connected by wide, component-side,
copper surface area. The use of vias and long traces to create LDO component connections is strongly
discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive
parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground
reference plane is also recommended and is either embedded in the printed circuit board (PCB) itself or located
on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the
output voltage, shields the LDO from noise, and functions similar to a thermal plane to spread (or sink) heat from
the LDO device when connected to the thermal pad. In most applications, this ground plane is necessary to meet
thermal requirements.
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the
board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the
GND pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to the
GND pin of the device.
10.2 Layout Example
(1)
Circles within thermal pad area indicate vias to other layers on the board, for electrical connections or thermal
conduction.
Figure 37. Fixed Voltage Layout
Copyright © 2006–2015, Texas Instruments Incorporated
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