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AM4376 Datasheet(PDF) 113 Page - Texas Instruments

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Part # AM4376
Description  AM437x Sitara??Processors
PDF  261 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM4376 Datasheet(HTML) 113 Page - Texas Instruments

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AM4376, AM4377, AM4378, AM4379
www.ti.com
SPRS851B – JUNE 2014 – REVISED APRIL 2015
Table 5-5. ADC0 Electrical Parameters (continued)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Internal Voltage Reference:
VDDA_ADC0 = 1.8 V
Spurious Free Dynamic
External Voltage Reference:
80
dB
Range
VREFP - VREFN = 1.8 V
Input Signal: 30 kHz sine wave at
-0.5 dB Full Scale
Internal Voltage Reference:
VDDA_ADC0 = 1.8 V
Signal-to-Noise Plus
External Voltage Reference:
69
dB
Distortion
VREFP - VREFN = 1.8 V
Input Signal: 30 kHz sine wave at
-0.5 dB Full Scale
VREFP and VREFN Input Impedance
20
k
Ω
Input Impedance of
f = input frequency
[1/((65.97 x 10-12) x f)]
Ω
AIN[7:0](2)
SAMPLING DYNAMICS
ADC Clock Frequency
13
MHz
ADC0
Conversion Time
13
clock
cycles
ADC0
Acquisition Time
2
257
clock
cycles
Sampling Rate(3)
ADC0 Clock = 13 MHz
867
kSPS
Channel-to-Channel Isolation
100
dB
TOUCHSCREEN SWITCH DRIVERS
Pullup and Pulldown Switch ON-Resistance (Ron)
2
Ω
Pullup and Pulldown Switch
Source impedance = 500
Ω
0.5
uA
Current Leakage Ileak
Drive Current
25
mA
Touchscreen Resistance
6
k
Ω
Pen Touch Detect
2
k
Ω
(1) The ADC0_VREFP and ADC0_VREFN terminals should not be allowed to float to prevent noise from coupling into the ADC. If
ADC0_VREFN is not used to connect an external negative voltage reference to the ADC, connect it to VSSA_ADC. If ADC0_VREFP is
not used to connect an external positive voltage reference to the ADC, connect it to VSSA_ADC or VDDA_ADC0. Connecting
ADC0_VREFP to VSSA_ADC in this use case is the preferred option because VDDA_ADC0 may couple more noise into the ADC than
VSSA_ADC.
(2) This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input.
(3) The maximum sample rate assumes a conversion time of 13 ADC clock cycles with the acquisition time configured for the minimum of 2
ADC clock cycles, where it takes a total of 15 ADC clock cycles to sample the analog input and convert it to a positive binary weighted
digital value.
Copyright © 2014–2015, Texas Instruments Incorporated
Specifications
113
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Product Folder Links: AM4376 AM4377 AM4378 AM4379



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