LM3102 datasheet(21/30 Pages) TI

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COUT

CIN

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VSUPPLY

LM3102, LM3102-Q1

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SNVS515H – SEPTEMBER 2007 – REVISED JUNE 2015

9 Power Supply Recommendations

The LM3102/-Q1 device is designed to operate from an input voltage supply range between 4.5 V and 42 V. This

input supply should be well regulated and able to withstand maximum input current and maintain a stable

voltage. The resistance of the input supply rail should be low enough that an input current transient does not

cause a high enough drop at the LM3102/-Q1 supply voltage that can cause a false UVLO fault triggering and

system reset. If the input supply is more than a few inches from the LM3102/-Q1, additional bulk capacitance

may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but

a 47-

μF or 100-μF electrolytic capacitor is a typical choice.

10 Layout

10.1 Layout Guidelines

The LM3102/-Q1 regulation, overvoltage, and current limit comparators are very fast so they will respond to short

duration noise pulses. Layout is therefore critical for optimum performance. It must be as neat and compact as

possible, and all external components must be as close to their associated pins of the LM3102/-Q1 as possible.

Refer to Layout Example, the loop formed by CIN, the main and synchronous MOSFET internal to the LM3102/-

Q1, and the PGND pin should be as small as possible. The connection from the PGND pin to CIN should be as

short and direct as possible. Vias should be added to connect the ground of CIN to a ground plane, located as

close to the capacitor as possible. The bootstrap capacitor CBST should be connected as close to the SW and

BST pins as possible, and the connecting traces should be thick. The feedback resistors and capacitor RFB1,

RFB2, and CFB should be close to the FB pin.

A long trace running from VOUT to RFB1 is generally acceptable because this is a low-impedance node. Ground

RFB2 directly to the AGND pin (pin 7). The output capacitor COUT should be connected close to the load and tied

directly to the ground plane. The inductor L should be connected close to the SW pin with as short a trace as

possible to reduce the potential for EMI (electromagnetic interference) generation.

If it is expected that the internal dissipation of the LM3102/-Q1 will produce excessive junction temperature

during normal operation, making good use of the PCB ground plane can help considerably to dissipate heat. The

exposed pad on the bottom of the LM3102/-Q1 IC package can be soldered to the ground plane, which should

extend out from beneath the LM3102/-Q1 to help dissipate heat.

The exposed pad is internally connected to the LM3102/-Q1 IC substrate. Additionally the use of thick traces,

where possible, can help conduct heat away from the LM3102/-Q1. Using numerous vias to connect the die

attached pad to the ground plane is a good practice. Judicious positioning of the PCB within the end product,

along with the use of any available air flow (forced or natural convection) can help reduce the junction

temperature.

10.2 Layout Example

Figure 31. Minimize Area of Current Loops in Buck Regulators

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