ADP3430 datasheet(8/26 Pages) ONSEMI

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ADP3430

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Theory of Operation

The ADP3430 combines a multi−mode, fixed frequency

PWM control with multiphase logic outputs for use in 2− or

3−phase synchronous buck CPU core supply power

converters. The internal VID DAC is designed to interface with

Intel 8−bit VRD/VRM 11.1 and compatible CPUs. Multiphase

operation is important for producing the high currents and low

voltages demanded by today’s microprocessors. Handling the

high currents in a single−phase converter places high thermal

demands on the components in the system, such as the

inductors and MOSFETs.

The multi−mode control of the ADP3430 ensures a stable,

high performance topology for the following:

• Balancing currents and thermals between phases for

both static and dynamic operation

• High speed response at the lowest possible switching

frequency and output decoupling

• FEPWM and TRDET functions for improved load step

and load release transient response

• Minimizing thermal switching losses by using lower

frequency operation

• Functions of with and without tight load line regulation

and accuracy

• Reduced output ripple due to multiphase cancellation

• PC board layout noise immunity

• Ease of use and design due to independent component

selection

• Flexibility in operation for tailoring design to low cost

or high performance

Startup Sequence

The ADP3430 follows the VR11.1 startup sequence

shown in Figure 5. After both the EN and UVLO conditions

are met, the DELAY pin goes through one cycle (TD1).

After this cycle, the internal oscillator is enabled. The first

four clock cycles are blanked from the PWM outputs and

used for phase detection as explained in the Phase Detection

Sequence section. Then, the soft−start ramp is enabled

(TD2), and the output comes up to the boot voltage of 1.1 V.

The boot hold time is determined by the DELAY pin as

it goes through a third cycle (TD3). During TD3, the

processor VID pins settle to the required VID code. When

TD3 is over, the ADP3430 reads the VID inputs and

soft−starts either up or down to the final VID voltage

(TD4).When TD4 and the PWRGD masking time (equal to

VID OTF masking) is completed, a third ramp on the

DELAY pin sets the PWRGD blanking (TD5).

Figure 5. System Startup Sequence

VTT I/O

(ADP3430 EN)

12 V

SUPPLY

UVLO

THRESHOLD

0.8 V

1.0 V

DELAY

VCC_CORE

VR READY

(ADP3430 PWRGD)

CPU

VID INPUTS

VID INVALID

VID VALID

VDELAY(TH)

(1.7 V)

VBOOT

(1.1 V)

VBOOT

(1.1 V)

VVID

TD1

TD2

TD4

TD5

50 s

TD3

Phase Number Configuration

The PSI pin is used as an input to determine the operating

phase number (2− or 3−phase), depending on power state of

the load. If this pin is set as low, the controller knows the load

is in a low power state and it pulls the ODN signal low, which

can be used to disable phase 3 (2−phase operation) for

increased efficiency. When PSI pin is set as high, then it

demands 3−phase operation. Please note that the PSI OTF

change is also supported.

The PWM outputs are logic−level devices intended for

driving fast response external gate drivers such as the

ADP3121 and ADP3122. Because each phase is monitored

independently, operation approaching 100% duty cycle is

possible. In addition, more than one PWM output can be on

at the same time to allow overlapping phases.

Master Clock Frequency

The clock frequency of the ADP3430 is set with an external

resistor connected from the RT pin to ground. The frequency

follows the graph in Figure 3. For both 2−Phase and 3−Phase

operations, the frequency per phase is equal to 1/6 of the clock

frequency.

Output Voltage Differential Sensing

The ADP3430 combines differential sensing with a high

accuracy VID DAC and reference, and a low offset error

amplifier. This maintains a worst−case specification of

± 8.0 mV differential sensing error over its full operating

output voltage and temperature range. The output voltage is

sensed between the FB pin and FBRTN pin. FB is connected

through a resistor to the regulation point, usually the remote

sense pin of the microprocessor. FBRTN is connected

directly to the remote sense ground point. The internal VID

DAC and precision reference are referenced to FBRTN,

which has a minimal current of 125

mA to allow accurate

remote sensing. The internal error amplifier compares the

output of the DAC to the FB pin to regulate the output

voltage.

ADP3430 Datasheet(PDF) 8 Page - ON Semiconductor

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