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ADP3430 Datasheet(PDF) 25 Page - ON Semiconductor |
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ADP3430 Datasheet(HTML) 25 Page - ON Semiconductor |
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25 / 26 page ![]() ADP3430 http://onsemi.com 25 current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. Signal Circuitry Recommendations The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB trace and FBRTN trace should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller. |
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