ADP3430 datasheet(18/26 Pages) ONSEMI

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ADP3430

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4. Compute the relative values for RCS1, RCS2, and

RTH using:

rCS2 +

(eq. 8)

(A * B)

r1 r2 * A (1 * B) r2 ) B (1 * A) r1

(1 * B)

r1 * B (1 * A) r2 * (A * B)

(eq. 9)

rCS1 +

(1 * A)

1*rCS2

r1*rCS2

(eq. 10)

rTH +

1*rCS2

* 1

rCS1

Calculate RTH = rTH × RCS, then select the closest value

of thermistor available. Also, compute a scaling factor (k)

based on the ratio of the actual thermistor value used relative

to the computed one.

k +

RTH(ACTUAL)

RTH(CALCULATED)

(eq. 11)

5. Calculate values for RCS1 and RCS2 using

Equation 12 and 13.

(eq. 12)

RCS1 + RCS k rCS1

(eq. 13)

RCS2 + RCS

(1 * k) ) k

rCS2

In this example, RCS is calculated to be 114 kW. Look for

an available 100 k

W thermistor, 0603 size. One such

thermistor is the Vishay NTHS0603N01N1003JR NTC

thermistor with A = 0.3602 and B = 0.09174. From these

values, rCS1 = 0.3795, rCS2 = 0.7195, and rTH = 1.075.

Solving for RTH yields 122.55 kW, so 100 kW is chosen,

making k = 0.816. Next, find RCS1 and RCS2 to be 35.3 kW

and 87.9 k

W. Finally, choose the closest 1% resistor values,

which yield a choice of 35.7 k

W and 88.7 kW.

COUT Selection

The required output decoupling for the regulator is

typically recommended by Intel for various processors and

platforms. Use some simple design guidelines to determine

the requirements. These guidelines are based on having both

bulk capacitors and ceramic capacitors in the system.

First, select the total amount of ceramic capacitance. This

is based on the number and type of capacitor to be used. The

best location for ceramic capacitors is inside the socket, with

12 to 18, 1206 size being the physical limit. Other capacitors

can be placed along the outer edge of the socket as well.

To determine the minimum amount of ceramic

capacitance required, start with a worst−case load step

occurring right after a switching cycle has stopped. The

ceramic capacitance then delivers the charge to the load

while the load is ramping up and until the VR has responded

with the next switching cycle.

Equation 14 gives the designer a rough approximation for

determining the minimum ceramic capacitance. Due to the

complexity of the PCB parasitics and bulk capacitors, the

actual amount of ceramic capacitance required can vary.

(eq. 14)

CZ(MIN) w

D Vrl

D IO

fSW

n * D *

D IO

2SR

The typical ceramic capacitors consist of multiple 10

or 22

mF capacitors. For this example, Equation 14 yields

132

mF, so six, 22 mF ceramic capacitors suffice. A lower

limit is based on meeting the capacitance for the load release

for a given maximum load step (

DIO) and a maximum

allowable overshoot.

(eq. 15)

CX(MIN) w

DIO

DVrl VVID

* CZ

This example uses 6, 22

mF 1206 MLC capacitors

(CZ = 132

mF), solving for the bulk capacitance yields.

CX(MIN) w

450 nH

56 A

50 mV

1.51875 V *

132 mF + 2.96mF

Using 7, 470

mF tantanium capacitors (KEMET) with a

typical ESR of 5 m

W each yields CX = 3.29 mF with an

RX = 0.7 m

One last check should be made to ensure that the ESL of

the bulk capacitors (LX) is low enough to limit the high

frequency ringing during a load change.

This is tested using:

(eq. 16)

LX v CZ RX 2 Q2

LX v 132 mF

0.7 mW

3 +

86.2 pH

where Q2 is limited to 4/3 to ensure a critically damped

system.

In this example, LX is approximately 70 pH for the 7,

tantanium capacitors, which satisfies this limitation. If LX

of the chosen bulk capacitor bank is too large, the number of

ceramic capacitors needs to be increased, or lower ESL

bulks need to be used if there is excessive undershoot during

a load transition.

Power MOSFETs

For this example, the N−channel power MOSFETs have

been selected for one high−side switch and two low−side

switches per phase. The main selection parameters for the

power MOSFETs are VGS(TH), QG, CISS, CRSS, and

RDS(ON). The minimum gate drive voltage (the supply

voltage to the ADP3120A dictates whether standard

threshold or logic−level threshold MOSFETs must be used.

With VGATE ~10 V, logic−level threshold MOSFETs

(VGS(TH) < 2.5 V) are recommended.

The maximum output current (IO) determines the RDS(ON)

requirement for the low−side (synchronous) MOSFETs.

With the ADP3430, currents are balanced between phases,

thus, the current in each low−side MOSFET is the output

current divided by the total number of MOSFETs (nSF).

With conduction losses being dominant, Equation 17 shows

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