ADP3430 datasheet(9/26 Pages) ONSEMI

9 / 26 page

ADP3430

http://onsemi.com

Output Current Sensing

The ADP3430 provides a dedicated current sense

amplifier (CSA) to monitor the total output current for

proper voltage positioning versus load current (when this

function is required), for the IMON output, and for current

limit detection. Sensing the load current at the output gives

the total real−time current being delivered to the load, which

is an inherently more accurate method than peak current

detection or sampling the current across a sense element

such as the low−side MOSFET. This amplifier can be

configured several ways, depending on the objectives of the

system, as follows:

• Output inductor DCR sensing without a thermistor for

lowest cost.

• Output inductor DCR sensing with a thermistor for

improved accuracy with tracking of inductor

temperature.

• Sense resistors for highest accuracy measurements.

The positive input of the CSA is connected to the

CSREF pin, which is connected to the average output

voltage. The inputs to the amplifier are summed together

through resistors from the sensing element, such as the

switch node side of the output inductors, to the inverting

input CSSUM. The feedback resistor between CSCOMP

and CSSUM sets the gain of the amplifier and a filter

capacitor is placed in parallel with this resistor. The gain of

the amplifier is programmable by adjusting the input

summing resistor.

An additional resistor divider connected between CSREF

and CSCOMP (with the midpoint connected to LLINE) can

be used to set the load line required by the microprocessor.

The current information is then given as CSREF − LLINE.

This difference signal is used internally to offset the

VID DAC for voltage positioning. The difference between

CSREF and CSCOMP is then used as a differential input for

the current limit comparator. This allows the load line to be

set independently of the current limit threshold. In the event

that the current limit threshold and load line are not

independent, the resistor divider between CSREF and

CSCOMP can be removed and the CSCOMP pin can be

directly connected to LLINE. To disable voltage positioning

entirely (that is, no load line) connect LLINE to CSREF.

To provide the best accuracy for sensing current, the CSA

is designed to have a low offset input voltage. Also, the

sensing gain is determined by external resistors to make it

extremely accurate.

Current Control Mode and Thermal Balance

The ADP3430 has individual inputs (SW1 to SW4) for

each phase that are used for monitoring the current of each

phase. This information is combined with an internal ramp

to create a current balancing feedback system that has been

optimized for initial current balance accuracy and dynamic

thermal balancing during operation. This current balance

information is independent of the average output current

information used for positioning as described in the Load

Line Setting section.

The magnitude of the internal ramp can be set to optimize

the transient response of the system. It also monitors the

supply voltage for feed−forward control for changes in the

supply. A resistor connected from the power input voltage

to the RAMP pin determines the slope of the internal PWM

ramp.

External resistors can be placed in series with individual

phases to create an intentional current imbalance if desired,

such as when one phase has better cooling and can support

higher currents. Resistor RSW1 through RSW4 can be used

for adjusting thermal balance. It is best to have the ability to

add these resistors during the initial design, therefore, ensure

that placeholders are provided in the layout.

To increase the current in any given phase, enlarge RSW

for that phase (make RSW = 0 for the hottest phase and do not

change it during balancing). Increasing RSW by 1 kW can

make an increase in phase current. Increase each RSW value

by small amounts to achieve balance, starting with the

coolest phase first.

Voltage Control Mode

A high gain, bandwidth voltage mode error amplifier is

used for the voltage mode control loop. The control input

voltage to the positive input is set via the VID logic

according to the voltages listed.

The output of the amplifier is the COMP pin, which sets

the termination voltage for the internal PWM ramps. The

main loop compensation is incorporated into the feedback

network between FB and COMP.

Fast Enhanced Transient Modes

The ADP3430 incorporates enhanced transient response

for both load steps and load release. For load steps, it senses

the error amp to determine if a load step has occurred and

sequences the proper number of phases on to ramp up the

output current.

For load release, it also senses the error amp and uses the

load release information to trigger the TRDET pin, which is

then used to adjust the feedback for optimal positioning

especially during high frequency load steps.

Additional information is used during load transients to

ensure proper sequencing and balancing of phases during

high frequency load steps as well as minimizing stress on the

components such as the input filter and MOSFETs.

Delay Timer

The delay times for the startup timing sequence are set

with a capacitor from the DELAY pin to ground. In UVLO,

or when EN is logic low, the DELAY pin is held at ground.

After the UVLO and EN signals are asserted, the first delay

time (TD1 in Figure 5) is initiated. A 15

mA current flows out

of the DELAY pin to charge CDLY. A comparator monitors

the DELAY voltage with a threshold of 1.7 V. The delay time

is therefore set by the 15

mA charging a capacitor from 0 V

ADP3430 Datasheet(PDF) 9 Page - ON Semiconductor

ADP3430 Datasheet(HTML) 9 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL