ADP3430 datasheet(11/26 Pages) ONSEMI

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ADP3430

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If the IMON and OCP are then desired to be changed based

on the TDC of the CPU, the ILIM resistor is the only

component that needs to be changed. If the IMON scaling is

the only desired change, then just changing the IMON resistor

accomplishes this.

The IMON pin also includes an active clamp to limit the

IMON voltage to 1.15 V MAX yet maintaining 1.0 V MIN

full−scale accurate reporting.

Power−Good Monitoring

The power−good comparator monitors the output voltage

via the CSREF pin. The PWRGD pin is an open−drain

output whose high level, when connected to a pullup

resistor, indicates that the output voltage is within the

nominal limits specified based on the VID voltage setting.

PWRGD goes low if the output voltage is outside of this

specified range, if the VID DAC inputs are in no CPU mode,

or if the EN pin is pulled low.

The PWRGD circuitry also incorporates an initial turn−on

delay time (TD5), based on the DELAY timer. Prior to the

SS voltage reaching the programmed VID DAC voltage and

the PWRGD masking−time finishing, the PWRGD pin is

held low. Once the SS pin is within 100 mV of the

programmed DAC voltage, the capacitor on the DELAY pin

begins to charge. A comparator monitors the DELAY

voltage and enables PWRGD when the voltage reaches

1.7 V. The PWRGD delay time is, therefore, set by a current

of 15

mA, charging a capacitor from 0 V to 1.7 V.

High Frequency Current Balance

Randomization for phases is implemented, in order to

prevent high frequency current/thermal imbalance due to

load and voltage regulator synchronization.

Power State Indicator

The PSI pin is used as an input to determine the operating

power state of the load. If this pin is pulled low, the controller

knows the load is in a low power state and it takes the ODN

signal low, which can be used to disable phases for increased

efficiency. PSI supports OTF change.

One additional feature of the ADP3430 is the internal

current limit threshold is changed when PSI is pulled low.

The current limit threshold is reduced by 2/3 such that the

same per phase average current limit is maintained to protect

the components in the system.

Figure 7. Efficiency Comparison (PSI High vs. Low)

(Vin = 12 V, Vo = 1.51875 V, Fs = 375 kHz)

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

2030

4050

6070

Load Current (A)

3−Phase (PSI High)

2−Phase (PSI Low)

Output Crowbar

To protect the load and output components of the supply,

the PWM outputs are driven low, which turns on the

low−side MOSFETs when the output voltage exceeds the

upper crowbar threshold. This crowbar action stops once the

output voltage falls below the release threshold of

approximately 375 mV.

Turning on the low−side MOSFETs pulls down the output

as the reverse current builds up in the inductors. If the output

overvoltage is due to a short in the high−side MOSFET, this

action current limits the input supply or blows its fuse,

protecting the microprocessor from being destroyed.

Output Enable and UVLO

For the ADP3430 to begin switching, the input supply

current to the controller must be higher than the UVLO

threshold and the EN pin must be higher than its 0.8 V

threshold. This initiates a system startup sequence. If either

UVLO or EN is less than their respective thresholds, the

ADP3430 is disabled. This holds the PWM outputs at

ground, shorts the DELAY capacitor to ground, and the

forces PWRGD and OD signals low.

In the application circuit, the OD pin should be connected

to the OD input of the external driver for the phase that is

always on (phase 1 and 2) while the ODN pin should be

connected to the OD input on the external drivers of the

phase 3. Grounding OD and ODN disable the drivers such

that both DRVH and DRVL are grounded. This feature is

important in preventing the discharge of the output

capacitors when the controller is shut off. If the driver

outputs are not disabled, a negative voltage can be generated

during output due to the high current discharge of the output

capacitors through the inductors.

Thermal Monitoring

The ADP3430 includes a thermal monitoring circuit to

detect when a point on the VR has exceeded a user−defined

temperature. The thermal monitoring circuit requires an

NTC thermistor to be placed between TTSNS and GND.

A fixed current of 123

mA is sourced out of the TTSNS pin

and into the thermistor. The current source is internally

limited to 5.0 V. An internal circuit compares the TTSNS

voltage to a 0.81 V threshold, and outputs an open−drain

signal at the VRHOT output. Once the voltage on the

TTSNS pin drops below its threshold, the open−drain output

asserts high to signal the system that an overtemperature

event has occurred. Because the TTSNS voltage changes

slowly with respect to time, 55 mV of hysteresis is built into

this comparator. The thermal monitoring circuitry does not

depend on EN and is active when UVLO is above its

threshold. When UVLO is below its threshold, VRHOT is

forced low.

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