ADP3430 datasheet(20/26 Pages) ONSEMI

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ADP3430

http://onsemi.com

where:

AR is the internal ramp amplifier gain.

AD is the current balancing amplifier gain.

RDS is the total low−side MOSFET on resistance.

CR is the internal ramp capacitor value.

Another requirement also needs to be satisfied:

IRAMP < ICLAMP (200 mA/3), thus:

(eq. 22)

RR w

VCC * VVID

ICLAMP

0.5

(12 * 1.51875) V

66.7 mA

+ 79 kW

Since above RR value is bigger than 79 kW, it keeps the

value of

750 KW.

The internal ramp voltage magnitude can be calculated by

using:

VR +

AR (1 * D) VVID

RR CR fSW

(eq. 23)

VR +

0.5

(1 * 0.1266)

1.51875 V

750 kW

5pF

300 kHz

+ 590 mV

The size of the internal ramp can be made larger or

smaller. If it is made larger, stability and noise rejection

improves, but transient degrades. Likewise, if the ramp is

made smaller, transient response improves at the sacrifice of

noise rejection and stability.

The factor of 3 in the denominator of Equation 21 sets a

ramp size that gives an optimal balance for good stability,

transient response, and thermal balance.

Comp Pin Ramp

A ramp signal on the COMP pin is due to the droop voltage

and output voltage ramps. This ramp amplitude adds to the

internal ramp to produce the following overall ramp signal

at the PWM input:

(eq. 24)

VRT +

1 *

1*n D

n fSW CX RO

In this example, the overall ramp signal is 0.862 V. If the

ramp size is smaller than 0.5 V, increase the ramp size to be

at least 0.5 V by decreasing the ramp resistor for noise

immunity.

Current Limit Setpoint

To select the current limit setpoint, first find the resistor

value for RLIM. The current limit threshold for the ADP3430

is set with a constant current source (IILIM = 4/3*IREF)

flowing out of the ILIM pin, which sets up a voltage (VLIM)

across RLIM. Thus, increasing RLIM now increases the

current limit. RLIM can be found using:

RLIM +

VLIM

IILIM

ILIM RCS DCR

VREF RPH

RREF

(eq. 25)

Here, ILIM is the peak average current limit for the supply

output. The peak average current is the dc current limit plus

the output ripple current. In this example, choose

ILIM_DC =82.8 A and having a ripple current of 10 A gives

an ILIM of 92.8 A. RCS is selected as 110 kW in this example,

RPH is 61.9 kW, DCR is 0.57 mW (assuming). This results in

an RLIM = 4.7 kW, for which 4.53 kW is chosen as the nearest

1% value.

The per−phase initial duty cycle limit and peak current

during a load step are determined by:

DMAX + D

VCOMP(MAX) * VBIAS

(eq. 26)

IPHMAX ^

DMAX

fSW

VIN * VVID

(eq. 27)

For the ADP3430, the maximum COMP voltage

(VCOMP(MAX)) is 4.4 V and the COMP pin bias voltage

(VBIAS) is 1.2 V. In this example, the maximum duty cycle

is 0.687 and the peak current is 53.3 A.

The limit of the peak per−phase current described earlier

during the secondary current limit is determined by:

IPHLIM ^

VCOMP(CLAMPED) * VBIAS

AD RDS(MAX)

(eq. 28)

For the ADP3430, the current balancing amplifier gain

(AD) is 5 and the clamped COMP pin voltage is 3.3 V. Using

an RDS(MAX) of 4.0 mW (low−side on resistance at 125°C)

results in a per−phase peak current limit of 100 A. This

current level can be reached only with an absolute short at

the output, and the current limit latchoff function shuts down

the regulator before overheating can occur.

IMON Setpoint

According to the function definition, IMON output voltage

should represent the load condition within the whole load

current range. The formula below will result RIMON in need:

RIMON +

VIMON

IIMON

VIMON RLIM

RCS

DCR

(eq. 29)

Here, IL is the total load current, M =10 is the current gain

for IMON. Since IMON output clamp voltage is around 1.1 V,

VIMON is selected as 0.8 V when IL = IMAX (69 A). While

RLIM = 4.53 kW, RIMON is calculated as 5.18 kW, for which

5.36 k

W is chosen as the nearest 1% value.

There is a capacitor (CIMON) in parallel with RIMON, in

order to filter output current ripple. The time constant of

RIMON * CIMON should be much bigger (> 10 x) than circuit

switching period. In this example, CIMON is selected as

2.2

mF.

Feedback Loop Compensation Design

Optimized compensation of the ADP3430 allows the best

possible response of the regulator output to a load change.

A type−three compensator on the voltage feedback is

adequate for proper compensation of the output filter.

Selecting Rfb = 1.24 kW, assuming Ca >> Cfb, compensator

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