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AS3649 Datasheet(PDF) 7 Page - ams AG

Part # AS3649
Description  2500mA High Current LED Flash Driver
PDF  39 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS3649 Datasheet(HTML) 7 Page - ams AG

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AS3649
Datasheet - Electrical Character i s t ics
www.ams.com/AS3649
1.0-2
7 - 39
Digital Interface
VIH
High Level Input Voltage
Pins ON, SCL, SDA.
and TXMASK/TORCH
1.26
VVIN
V
VIL
Low Level Input Voltage
0.0
0.54
V
VIHFLASH
High Level Input Voltage
Pin STROBE.
0.84
VVIN
V
VILFLASH
Low Level Input Voltage
0.0
0.54
V
VOL
Low Level Output Voltage
Pin SDA, IOL=3mA
0.3
V
ILEAK
Leakage current
Pins ON, SCL, SDA
-1.0
0.0
+1.0
µA
IPD
Pulldown current to GND
5
Pins STROBE and TXMASK/TORCH
36
µA
tDEBTORCH
TORCH debounce time
6.3
9
11.7
ms
tDEBTXMASK TXMASK debounce timer
1.5
µs
I
2C mode timings - see Figure 3 on page 8
fSCLK
SCL Clock Frequency
0
400
kHz
tBUF
Bus Free Time Between a
STOP and START
Condition
1.3
µs
tHD:STA
Hold Time (Repeated)
START Condition
6
0.6
µs
tLOW
LOW Period of SCL Clock
1.3
µs
tHIGH
HIGH Period of SCL Clock
0.6
µs
tSU:STA
Setup Time for a Repeated
START Condition
0.6
µs
tHD:DAT
Data Hold Time
7
00.9
µs
tSU:DAT
Data Setup Time
8
100
ns
tR
Rise Time of Both SDA and
SCL Signals
20 +
0.1CB
300
ns
tF
Fall Time of Both SDA and
SCL Signals
20 +
0.1CB
300
ns
tSU:STO
Setup Time for STOP
Condition
0.6
µs
CB
Capacitive Load for Each
Bus Line
CB — total capacitance of one bus line in pF
400
pF
CI/O
I/O Capacitance (SDA,
SCL)
10
pF
1. To improve efficiency at low output currents, the active part of the internal switching transistor PMOS is reduced in size to 1/5 its original
size. This reduces the current required to drive the PMOS transistor and therefore improves overall efficiency at low output currents.
2. The maximum current driving capability depends on supply voltage VVIN, LED forward voltage and coil peak current limit.
3. Due to slope compensation of the current limit, ILIMIT changes with duty cycle - see Figure 16 on page 11.
4. Accuracy defined in % of current setting and in absolute value (µA), accuracy values have to be added together
5. A pulldown current of 36µA is equal to a pulldown resistor of 42k
 at 1.5V
6. After this period, the first clock pulse is generated
7. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
8. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of
the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.
Table 3. Electrical Characteristics (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit



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