AS3649

Datasheet - Application In form atio n

www.ams.com/AS3649

1.0-2

35 - 39

9.2 PCB Layout Guideline

The high speed operation requires proper layout for optimum performance. Route the power traces first and try to minimize the area and wire

length of the two high frequency/high current loops:

At the pin GND a single via (or more vias, which are closely combined) connects to the common ground plane. This via(s) will isolate the DCDC

high frequency currents from the common ground (as most high frequency current will flow between Loop1 and Loop2 and will not pass the

ground plane) - see the ‘island’ in Figure 31.

Figure 31. Layout Recommendation

Note: If component placement rules allow, move all components close to the AS3649 to reduce the area and length of Loop1 and Loop2.

It is recommended to use the main ground plane for the LED ground connections (improved thermal performance of the LEDs) - it is

recommend to use a separate ground line as shown Figure 31 for the ground connection of the NTC (this avoids errors for the temper-

ature measurement of the LEDs due to the high LED current in the main ground plane).

Keep the LED path (from pin LED_OUT1/2 to the LED and the ground return path) below 10cm (represents an inductance of less than

100nH).

frequency noise for the power supply of AS3649. This capacitor should be as close as possible to the AGND/VIN pins of AS3649.

 

 

    

 

 

   



  

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