AS3649

Datasheet - Detailed Descr i p ti on

www.ams.com/AS3649

1.0-2

20 - 39

period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of

data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between

START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each

receiver acknowledges with a ninth bit.

device must generate an extra clock pulse that is associated with this acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW

during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must

signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the

slave must leave the data line HIGH to enable the master to generate the STOP condition.

Figure 27. Data Transfer on I

Depending upon the state of the R/W bit, two types of data transfer are possible:

1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next

follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most

significant bit (MSB) first.

2. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then

returns an acknowledge bit, followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all

received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device

generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a

repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released.

Data is transferred with the most significant bit (MSB) first.

The AS3649 can operate in the following two modes:

1. Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an

acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address

recognition is performed by hardware after reception of the slave address and direction bit (see Figure 28). The slave address byte is

the first byte received after the master generates the START condition. The slave address byte contains the 7-bit AS3649 address,

which is 0110000, followed by the direction bit (R/W), which, for a write, is 0.

device outputs an acknowledge on the SDA line. After the AS3649 acknowledges the slave address + write bit, the master transmits a

SLAVE

ADDRESS

ACKNOWLEDGEMENT SIG-

NAL FROM RECEIVER

ACKNOWLEDGEMENT SIG-

NAL FROM RECEIVER

REPEATED IF MORE

BYTES ARE TRANS-

FERRED

STOP CONDITION

OR REPEATED

START CONDITION

START

CONDITION

SCL

SDA

MSB

R/W

DIRECTION

BIT

ACK

1

2

6

78

9

1

2

3-7

89