DLPC200

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DLPS014E – APRIL 2010 – REVISED AUGUST 2014

6.5 I/O Electrical Characteristics

All inputs and outputs are LVCMOS

TEST CONDITIONS

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Input LVCMOS

–0.3

2.25

V

Input LVCMOS

–0.3

0.7

1.7

V

Input LVCMOS

–0.3

0.8

1.7

3.6

V

Input LVTTL

–0.3

0.8

1.7

3.6

V

Output LVCMOS

0.45

V

Output LVTTL

2.4

0.45

V

Output LVCMOS

0.2

V

Output LVDS

0.3

V

Output SSTL-18

1.484

0.398

V

Class I

Bidirectional SSTL-

0.844

1.094

1.484

0.398

V

18 Class I

Bidirectional

–0.3

0.8

1.7

3.6

0.2

V

LVCMOS

(1)

Cross reference to I/O assignments

6.6 Video Input Pixel Interface Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Clock frequency, PORTx_CLK

80

MHz

Pulse duration, high

45% to 55% reference points (signal)

5.6

ns

Pulse duration, low

45% to 55% reference points (signal)

5.6

ns

Setup time, PORTx_D(23–0) valid before PORTx_CLK

1.5

ns

Hold time, PORTx_D(23–0) valid after PORTx_CLK

1.5

ns

Setup time, PORTx_VSYNC valid before PORTx_CLK

1.5

ns

Hold time, PORTx_VSYNC valid after PORTx_CLK

1.5

ns

Setup time, PORTx_HSYNC valid before PORTx_CLK

1.5

ns

Hold time, PORTx_HSYNC valid after PORTx_CLK

1.5

ns

Setup time, PORTx_IVALID valid before PORTx_CLK

1.5

ns

Hold time, PORTx_IVALID valid after PORTx_CLK

1.5

ns

(1)

PCLK may be inverted from that shown in Figure 1. In that case, the same specifications in the table are valid except now referenced to

the falling edge of the clock. If the falling edge of PCLK is used, a USB or SPI command must be sent to tell the DLPC200 to use the

falling edge of PCLK.

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