DLPC200 datasheet(36/52 Pages) TI1

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DLPC200

DLPS014E – APRIL 2010 – REVISED AUGUST 2014

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Feature Description (continued)

Table 1. Frame Rates

MODE

MIN

MAX

UNIT

1 bit per pixel

5000

Structured light

8 bits per pixel

700

Video

7.4 Device Functional Modes

The DLPC200 has two basic functional mode types: video and structured light.

7.4.1 Video Modes

The controller accepts RGB-8-8-8 input to port 1 or port 2 through a selectable MUX. XGA video information is

displayed on the DMD at 6 to 60 fps.

An internal pattern generator can generate RGB-8-8-8 video patterns into an internal selectable MUX for

verification and debug purposes.

7.4.2 Structured Light Modes

The DLPC200 provides two structured light modes: static image buffer and real-time structured light.

7.4.2.1 Static Image Buffer Mode

Image data can be loaded into parallel flash memory to load to DDR2 memory at startup to be displayed, or can

be loaded over USB or the SPI port directly to DDR2 memory to be displayed. Binary (1-bit) or grayscale (8-bit)

patterns can be displayed. The memory will hold 960 binary patterns or 120 grayscale patterns.

7.4.2.2 Real Time Structured Light Mode

RGB-8-8-8 60 fps data can be input into port 1 or port 2 and reinterpreted as up to 24 binary (1-bit) patterns or

three grayscale (8-bit) patterns. The specified number of patterns is displayed equally during the exposure time

specified. Any unused RGB-8-8-8 data in the video frame must be filled with data, usually 0s.

For example, during one video frame (16.67 ms), 12 binary patterns of the 24 RGB bits are requested to be

displayed during half of the video frame time (exposure time = 8.33 ms). Each of the eight red bits and the four

most significant green bits are displayed as a binary pattern for 694 µs each. The remaining bits are ignored and

the remaining 8.33 ms of the frame will be dark.

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