DLPC200 datasheet(12/52 Pages) TI1

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DLPC200

DLPS014E – APRIL 2010 – REVISED AUGUST 2014

www.ti.com

Pin Functions (continued)

I/O

CLOCK SYSTEM

DESCRIPTION

TYPE(1)

NAME

NUMBER

SDRAM INTERFACE (CONTINUED)

MEM_A0

AD24

MEM_A1

AF21

MEM_A2

AG23

MEM_A3

AE8

MEM_A4

AG12

MEM_A5

AF23

MEM_A6

AC17

DDR2 memory, multiplexed row and column address. The memory

MEM_A7

AA16

in the kit is 512 Mb in ×16 mode, 8 Meg × 16 bits × 4 banks. Only

MEM_CLK

A(12:0) and BA(1:0) are currently used. A(15:13) and BA(2) are

MEM_A8

AE23

reserved for future use (RFU).

MEM_A9

AE22

MEM_A10

AE16

MEM_A11

AD25

MEM_A12

AF19

MEM_A13

AH10

MEM_A14

AA8

MEM_A15

AD11

MEM_CAS

AG19

MEM_CLK

Column address strobe, active low

MEM_RAS

AE20

MEM_CLK

Row address strobe, active low

MEM_CS0

AF13

MEM_CLK

Chip select, active low

MEM_WE

AG25

MEM_CLK

Write enable, active low

MEM_ODT

AH12

MEM_CLK

MEM_DM0

MEM_CLK

MEM_DM1

AE2

MEM_CLK

MEM_DM2

AH6

MEM_CLK

MEM_DM3

AF7

MEM_CLK

MEM_DM4

AE13

MEM_CLK

MEM_DM5

AH18

MEM_CLK

MEM_DM6

AF24

MEM_CLK

MEM_DM7

AG26

MEM_CLK

MEM_DS0

AB2

MEM_CLK_P0

MEM_DS1

AE3

MEM_CLK_N0

MEM_DS2

AD7

MEM_CLK_P1

MEM_DS3

AE10

MEM_CLK_N1

MEM_DS4

AF11

MEM_CLK_P2

MEM_DS5

AF17

MEM_CLK_N2

MEM_DS6

AE18

MEM_CLK_P3

MEM_DS7

AF26

MEM_CLK_N3

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