DLPC900

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DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

4 Revision History

Changes from Original (October 2014) to Revision A

Page

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Changed phrasing of pattern speed features ......................................................................................................................... 1

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Corrected the width of the input pixel ports to 24-bits ............................................................................................................ 1

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Added I/O Type and Subscript Definition table ...................................................................................................................... 5

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Corrected maximum port width of Ports 1 and 2 in table note ............................................................................................. 10

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Updated ESD Ratings table title and value column ............................................................................................................. 20

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ESD sensitivity machine model was removed...................................................................................................................... 20

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Added note to clarify that Ports 1 and 2 are used as 24-bit buses ...................................................................................... 29

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Changed section title to correct bus size to 48-bits.............................................................................................................. 30

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Removed references to 30-bit RGB video............................................................................................................................ 36

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Corrected minor typos .......................................................................................................................................................... 38

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Corrected video pattern mode timing diagram and description............................................................................................ 39

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Corrected pre-stored pattern mode timing diagram and description .................................................................................... 39

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Corrected pre-stored pattern mode 3 pattern example diagram and description................................................................. 39

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Removed Allowed Pattern Combinations table .................................................................................................................... 40

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Added Minimum Exposure in Any Pattern Mode table......................................................................................................... 40

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Added Minimum Exposures for Number of Active DMD Blocks table.................................................................................. 40

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Updated Boot Flash Memory Layout image to reflect firmware version 2.0 ........................................................................ 42

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Added note about firmware components.............................................................................................................................. 43

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Corrected video data interface size to 24-bits ...................................................................................................................... 43

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Corrected video mode port maximum size to 24 bits ........................................................................................................... 44

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Corrected P1 and P2 signal description regarding 24-bit bus width .................................................................................... 44

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Corrected spacing and formatting ........................................................................................................................................ 51

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Corrected minor typo ............................................................................................................................................................ 60

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Changed the number of P1 and P2 lines to reflect 24 bit-width........................................................................................... 61

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