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DLPC900ZPC Datasheet(PDF) 13 Page - Texas Instruments |
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DLPC900ZPC Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 72 page  DLPC900 www.ti.com DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015 Peripheral Interface Pin Functions (continued) PIN I/O I/O TYPE CLK SYSTEM DESCRIPTION POWER NAME NUMBER I2C bus 2, clock. This bus supports 400 kHz, fast mode operation. This input is not 5 V tolerant. This pin requires I2C2_SCL (1) B22 VDD33 B2 N/A an external pullup resistor to 3.3 V. The minimum acceptable pullup value is 1 k Ω resistor. SSP0_CLK AD4 VDD33 B5 N/A Synchronous serial port 0, clock SSP0_RXD AD5 VDD33 I4 SSP0_CLK Synchronous serial port 0, receive data in SSP0_TXD AB7 VDD33 O5 SSP0_CLK Synchronous serial port 0, transmit data out SSP0_CSZ_0 (1) AC5 VDD33 B5 SSP0_CLK Synchronous serial port 0, chip select 0 (active low) SSP0_CSZ_1 (1) AB6 VDD33 B5 SSP0_CLK Synchronous serial port 0, chip select 1 (active low) SSP0_CSZ_2 (1) AC3 VDD33 B5 SSP0_CLK Synchronous serial port 0, chip select 2 (active low) UART0, UART transmit data output. The firmware only UART0_TXD AB3 VDD33 O5 Async outputs debug messages on this port. UART0, UART receive data input. The firmware does not UART0_RXD AD1 VDD33 I4 Async support receiving data on this port. UART0, UART ready to send hardware flow control output UART0_RTSZ AD2 VDD33 O5 Async (active low) UART0, UART clear to send hardware flow control input UART0_CTSZ AE2 VDD33 I4 Async (active low). This pin requires an external 10 k Ω pulldown resistor. USB_DAT_N (1) C5 USB D– I/O VDD33 B9 Async USB_DAT_P D6 USB D+ I/O Boot mode. When this pin is held low, the firmware boots- up in bootload mode. When pin is held high, the firmware HOLD_BOOTZ F24 VDD33 B2 Async boots-up in normal operating mode. This pin requires an external 1 k Ω pullup resistor. The firmware will use this pin to enable an external buffer USB_ENZ (1) E25 VDD33 B2 Async on the USB data lines after it has completed initialization. FAULT_STATUS AC11 VDD33 O2 Async This signal toggles or held high to indicate status faults. This signal toggles to indicate the system is operational. HEARTBEAT AB12 VDD33 O2 Async Period is ~1second. This signal serves as an interrupt for pattern sequencing SEQ_INT2 H26 VDD33 I2 Async and must be connected to SEQ_AUX6. This signal serves as an interrupt for pattern sequencing SEQ_INT1 G26 VDD33 I2 Async and must be connected to SEQ_AUX7. This signal serves as an interrupt for pattern sequencing SEQ_AUX7 F26 VDD33 O2 Async and must be connected to SEQ_INT1. This signal serves as an interrupt for pattern sequencing SEQ_AUX6 E26 VDD33 O2 Async and must be connected to SEQ_INT2. On DLP® LightCrafter 9000 EVM, this pin connects to TEST_FUNC_5 (1) K22 VDD33 B2 Async FPGA and could serve as a configuration pin. Otherwise can be left unconnected. On DLP LightCrafter 9000 EVM, this pin connects to FPGA TEST_FUNC_4 (1) J26 VDD33 B2 Async and could serve as a configuration pin. Otherwise can be left unconnected. On DLP LightCrafter 9000 EVM, this pin connects to FPGA and serves as a configuration pin. This function configures TEST_FUNC_3 (1) J25 VDD33 B2 Async the 24-bit parallel data output of the FPGA to be split between the master and the slave controllers. The firmware will set this pin high by default. On DLP LightCrafter 9000 EVM, this pin connects to FPGA TEST_FUNC_2 (1) J24 VDD33 B2 Async and could serve as a configuration pin. Otherwise can be left unconnected. On DLP LightCrafter 9000 EVM, this pin connects to FPGA TEST_FUNC_1 (1) J23 VDD33 B2 Async and could serve as a configuration pin. Otherwise can be left unconnected. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: DLPC900 |
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