DLPC900ZPC datasheet(49/72 Pages) TI1

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DLPC900

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DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

System Power Regulation (continued)

9.1.1.2 1.8-V System Power

The DLPC900 power delivery system provides two independent 1.8-V power sources. One of the 1.8-V power

sources should be used to supply 1.8-V power to the DLPC900 LVDS I/O and internal DRAM. Power for these

functions should always be fed from a common source, which is recommended as a linear regulator. The second

1.8-V power source should be used (along with appropriate filtering as discussed in the PCB Layout Guidelines

for Internal Controller PLL Power ) to supply all of the DLPC900 internal PLLs (PLLD_VAD, PLLM1_VAD, and

PLLM2_VAD). To keep this power as clean as possible, a dedicated linear regulator is highly recommended for

the 1.8-V power to the PLLs.

9.1.1.3 3.3-V System Power

The DLPC900 can support a low-cost power delivery system with a single 3.3-V power sources derived from a

switching regulator. This 3.3-V power will supply all LVTTL I/O and the crystal oscillator cell. The 3.3-V power

should remain active in all power modes for which 1.15-V core power is applied.

9.2 System Environment and Defaults

9.2.1 DLPC900 System Power-Up and Reset Default Conditions

Following system power-up, the DLPC900 will perform a power-up initialization routine that will default the

controller to its normal power mode in which all blocks are powered, all processor clocks will be enabled at their

full rate and associated resets will be released. Most other clocks will default disabled with associated resets

asserted until released by the processor. These same defaults will also be applied as part of all system reset

events that occur without removing or cycling power. The 1.8-V power should be applied prior to releasing the

reset so that the LVDS I/O and the internal embedded DRAM are enabled before the DLPC900 begins executing

its system initialization routines.

9.3 System Power-Up Sequence

Although the DLPC900 requires an array of power supply voltages, for example, 1.15 V, 1.8 V, and 3.3 V, there

are no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC900, as

long as the system is held in reset during power supply sequencing. This is true for both power-up (reset

controlled by POSENSE) and power-down (reset controlled by PWRGOOD) scenarios. Similarly, there is no

minimum time between powering-up or powering-down the different supplies feeding the DLPC900. However,

power-sequencing requirements are common for the devices that share the supplies with the DLPC900.

Power-sequencing recommendations to ensure proper operation are:

•

1.15-V core power should be applied whenever any I/O power is applied. This ensures the state of the

associated I/O that are powered are set to a know state. Thus, applying core power first is recommended.

•

All DLPC900 power should be applied before POSENSE is asserted to ensure proper power-up initialization

is performed.

It is assumed that all DLPC900 power-up sequencing is handled by external hardware. It is also assumed that an

external power monitor will hold the DLPC900 in system reset during power-up (that is, POSENSE = 0). During

this time all controller I/O's will be tri-stated. The master PLL (PLLM1) will be released from reset upon the low-

to-high transition of POSENSE, but the DLPC900 will be kept in for an additional 60 ms to allow the PLL to lock

and stabilize its outputs. After this delay the DLPC900 internal resets will be deasserted, thus causing the

processor to begin its boot-up routine.

Figure 25 shows the recommended DLPC900 system power-up sequence of the regulators:

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