DLPC900ZPC datasheet(45/72 Pages) TI1

45 / 72 page

DLPC900

www.ti.com

DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

Table 8. Active Signals - Illumination Interface

SIGNAL NAME

DESCRIPTION

HEARTBEAT

Signal toggles continuously to indicate system is running fine.

FAULT_STATUS

Signal toggles or held high indicating system faults

RED_LED_EN

Red LED enable

GRN_LED_EN

Green LED enable

BLU_LED_EN

Blue LED enable

RED_LED_PWM

Red LED PWM signal used to control the LED current

GRN_LED_PWM

Green LED PWM signal used to control the LED current

BLU_LED_PWM

Blue LED PWM signal used to control the LED current

8.2.1.2.1.3.2

Trigger and Sync Interface

The DLPC900 outputs a trigger signal for synchronizing displayed patterns with a camera, sensor, or other

peripherals. The sync output supporting signals are: horizontal sync, vertical sync, two input triggers, and two

output triggers. Depending on the application, these signals control how the pattern is displayed.

Table 9. Active Signals - Trigger and Sync Interface

SIGNAL NAME

DESCRIPTION

P1_HSYNC

Horizontal Sync

P1_VSYNC

Vertical Sync

TRIG_IN_1

Depending on the mode, advances the pattern display.

TRIG_IN_2

Depending on the mode, starts or stops the pattern display.

TRIG_OUT_1

Active high during pattern exposure

TRIG_OUT_2

Active high pulse to indicate first pattern display

8.2.1.2.1.4

DLPC900 System Support Interfaces

8.2.1.2.1.4.1

Reference Clock and PLL

The DLPC900 controller requires a 20-MHz 3.3-V external input from an oscillator. This signal serves as the

DLPC900 chipset reference clock from which the majority of the interfaces derive their timing. This includes DMD

interfaces and serial interfaces.

Refer to PCB Layout Guidelines for Internal Controller PLL Power on PLL guidelines.

8.2.1.2.1.4.2

Program Memory Flash Interface

The DLPC900 provides three external program memory chip selects for standard NOR-type flash:

•

PM_CSZ_0 – flash device (

≤ 128 Mb)

•

PM_CSZ_1 – dedicated CS for boot flash device (

≤ 128 Mb). Refer to the Figure 21 for the memory layout of

the boot flash.

•

PM_CSZ_2 – flash device (

≤ 128 Mb)

Flash access timing is programmable up to 19 wait-states. Table 10 contains the formulas to calculate the

required wait-states for each of the parameters shown in Figure 22 for a typical flash device. Refer to the

DLPC900 Programmers Guide for details on how to set new wait-state values.

Table 10. Flash Wait-States

PARAMETER

FORMULA (1)

DEFAULT

TCS (CSZ low to WEZ low )

= Roundup((TCS+ 5 ns) / 6.7 ns)

TWP (WEZ low to WEZ high)

= Roundup((TWP+ 5 ns) / 6.7 ns)

TCH (WEZ high to CSZ high )

= Roundup((TCH+ 5 ns) / 6.7 ns)

(1)

Assumes a maximum single direction trace length of 75 mm.

Submit Documentation Feedback

Product Folder Links: DLPC900

DLPC900ZPC Datasheet(PDF) 45 Page - Texas Instruments

DLPC900ZPC Datasheet(HTML) 45 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL