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DLPC900ZPC Datasheet(PDF) 15 Page - Texas Instruments |
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DLPC900ZPC Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 72 page ![]() DLPC900 www.ti.com DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015 LED Control Pin Functions (continued) PIN (1) I/O I/O TYPE CLK SYSTEM DESCRIPTION POWER NAME NUMBER BLU_LED_EN D24 VDD33 O2 Async Blue LED enable signal. GRN_LED_EN C25 VDD33 O2 Async Green LED enable signal. RED_LED_EN B26 VDD33 O2 Async Red LED enable signal. Two Controller Support Pin Functions PIN I/O I/O TYPE CLK SYSTEM DESCRIPTION (1) POWER NAME NUMBER Sequence sync. This signal must be connected between the master and slave controller in a two controller configuration. SEQ_SYNC AB9 VDD33 B3 Async Do not leave unconnected. This pin requires an external 10- k Ω pullup resistor. This signal is used by the master controller to communicate SSP0_CSZ4_SLV U26 VDD33 B2 SSP0_CLK with the slave controller over the SSP interface. This pin requires an external 4.7-k Ω pullup resistor FSD12_OUTPUT T23 VDD33 B2 Async This pin must be connected to DA_SYNC_INPUT (2) DA_SYNC_INPUT R22 VDD33 B2 Async This pin must be connected to FSD12_OUTPUT (3) This signal must be connected between the master and slave controller in a two controller configuration. The slave SLV_CTRL_PRST V25 VDD33 B2 Async controller will pull this signal high to inform the master controller that it is present and ready. This pin requires an external 10-k Ω pulldown resistor. Do not leave unconnected. When this pin is high, the controller operates as the master CTRL_MODE_CF controller. When this pin is low the controller operates as the V26 VDD33 B2 Async G slave controller. Use an external 4.7-k Ω pullup or pulldown resistor to identify the controller. Do not leave unconnected. (1) Refer to the Typical Single Controller Chipset and the Typical Two Controller Chipset for a description between a one controller and a two controller configuration. (2) The FSD12_OUTPUT of the slave controller must be left unconnected. (3) The DA_SYNC_INPUT of the slave controller must be connected to the FSD12_OUTPUT of the master controller. Reserved Pin Functions PIN I/O I/O TYPE CLK SYSTEM DESCRIPTION POWER NAME NUMBER Reserved. This pin requires an external 4.7-k Ω pullup AFE_ARSTZ AC12 VDD33 O2 Async resistor. RESERVED_AD12 AD12 VDD33 O6 N/A Reserved. Should be left unconnected. AFE_IRQ AB13 VDD33 I 4 Async Reserved. Should be left unconnected. RESERVED_AF11 AF11 VDD33 I4 N/A Reserved. Should be left unconnected. RESERVED_AD11 AD11 VDD33 I4 N/A Reserved. Should be left unconnected. RESERVED_AE11 AE11 VDD33 I4 N/A Reserved. Should be left unconnected. Reserved. This pin requires an external 10-k Ω pullup RESERVED_AE8 AE8 VDD33 I4 N/A resistor. RESERVED_AD8 AD8 VDD33 O5 N/A Reserved. Should be left unconnected. RESERVED_AC9 AC9 VDD33 O5 N/A Reserved. Should be left unconnected. Reserved. This pin Requires an external 10-k Ω pulldown RESERVED_AF8 AF8 VDD33 I4 N/A resistor. RESERVED_E3 E3 VDD33 B5 N/A Reserved. Should be left unconnected. RESERVED_AB10 AB10 VDD33 B2 N/A Reserved. Should be left unconnected. RESERVED_AD9 AD9 VDD33 B2 N/A Reserved. Should be left unconnected. RESERVED_AE9 AE9 VDD33 B2 N/A Reserved. Should be left unconnected. RESERVED_AF9 AF9 VDD33 B2 N/A Reserved. Should be left unconnected. RESERVED_AB11 AB11 VDD33 B2 N/A Reserved. Should be left unconnected. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: DLPC900 |
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