DLPC900ZPC datasheet(52/72 Pages) TI1

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0.1 2F

100 2F

0.1 2F

R=0.36

0.1 2F

Vcore

1.15 PLL1

1.15 PLL2

1.15 PLL3

VPLL

DLPC900

Regulator

Vout

GND

1.15V

GND

DLPC900

DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

www.ti.com

10 Layout

10.1 Layout Guidelines

10.1.1 General PCB Recommendations

Two-ounce copper planes are recommended in the PCB design in order to achieve needed thermal connectivity.

10.1.2 PCB Layout Guidelines for Internal Controller PLL Power

The following are guidelines to achieve desired controller performance relative to internal PLLs:

The DLPC900 contains four PLLs (PLLM1, PLLM2, PLLD, and PLLS), each of which have a dedicated 1.15 V

digital supply; three of these PLLs (PLLM1, PLLM2, and PLLD) have a dedicated 1.8 V analog supply. It is

important to have filtering on the supply pins that covers a broad frequency range. Each 1.15 V PLL supply pin

should have individual high frequency filtering in the form of a ferrite bead and a 0.1 µF ceramic capacitor. These

components should be located very close to the individual PLL supply balls. The impedance of the ferrite bead

should far exceed that of the capacitor at frequencies above 10 MHz. The 1.15 V to the PLL supply pins should

also have low frequency filtering in the form of an RC filter. This filter can be common to all the PLLs. The

voltage drop across the resistor is limited by the 1.15 V regulator tolerance and the DLPC900 voltage tolerance.

A resistance of 0.36

Ω and a 100 µF ceramic are recommended. Figure 26 shows the recommended filter

topology.

Figure 26. Recommended Filter Topology for PLL 1.15-V Supplies

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DLPC900ZPC Datasheet(PDF) 52 Page - Texas Instruments