DLPC900ZPC datasheet(57/72 Pages) TI1

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DLPC900

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DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015

10.1.8 DMD Interface Considerations

High-speed interface waveform quality and timing on the DLPC900 controller (that is, the LVDS DMD interface)

is dependent on the following factors:

•

Total length of the interconnect system

•

Spacing between traces

•

Characteristic impedance

•

Etch losses

•

How well matched the lengths are across the interface

Thus, ensuring positive timing margin requires attention to many factors.

As an example, DMD interface system timing margin can be calculated as follows:

Setup Margin = (controller output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation)

(4)

Hold-time Margin = (controller output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation)

(5)

The PCB SI degradation is the signal integrity degradation due to PCB affects which includes such things as

simultaneously switching output (SSO) noise, crosstalk, and intersymbol interference (ISI) noise.

DLPC900 I/O timing parameters, as well as DMD I/O timing parameters, can be easily found in their

corresponding data sheets. Similarly, PCB routing mismatch can be easily budgeted and met via controlled PCB

routing. However, PCB SI degradation is not as easy-to-determine.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design

guidelines provide a reference of an interconnect system that satisfies both waveform quality and timing

requirements (accounting for both PCB routing mismatch and PCB SI degradation). Deviation from these

recommendations may work, but should be confirmed with PCB signal integrity analysis or lab measurements.

PCB design: Refer to the Figure 30.

Configuration:

Asymmetric dual stripline

Etch thickness (T):

1.0-oz copper (1.2 mil)

Flex etch thickness (T):

0.5-oz copper (0.6 mil)

Single-ended signal impedance:

Ω (±10%)

Differential signal impedance:

100

Ω (±10%)

PCB stackup: Refer to the Figure 30.

Reference plane 1 is assumed to be a ground plane for proper return path.

Reference plane 2 is assumed to be the I/O power plane or ground.

Dielectric FR4, (Er):

4.2 (nominal)

Signal trace distance to reference plane 1 (H1): 5.0 mil (nominal)

Signal trace distance to reference plane 2 (H2): 34.2 mil (nominal)

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