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LAN8820I Datasheet(PDF) 36 Page - Microchip Technology |
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LAN8820I Datasheet(HTML) 36 Page - Microchip Technology |
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36 / 83 page ![]() LAN8820/LAN8820I DS00001871B-page 36 2009-2015 Microchip Technology Inc. 4.2.1 BASIC CONTROL REGISTER Note 4-1 The default is determined by the CONFIG[3:2] pins as described in Section 3.8.1.2.3, "Configuration Bits Impacted by the Mode of Operation," on page 26“ Index (In Decimal): 0 Size: 16 bits Bits Description Type Default 15 PHY Soft Reset (RESET) 1 = PHY software reset. This bit is self-clearing. When setting this bit, do not set other bits in this register. The configuration is set from the register bit values as described in Section 3.6.2, "Software Reset," on page 22. Note: The PHY will be in the normal mode after a PHY software reset. R/W SC 0b 14 Loopback 0 = normal operation 1 = loopback mode R/W 0b 13 Speed Select[0] Together with Speed Select[1], sets speed per the following table: [Speed Select1][Speed Select 0] 00 = 10Mbps 01 = 100Mbps 10 = 1000Mbps 11 = Reserved Note: Ignored if the Auto-Negotiation Enable bit of this register is 1. R/W Note 4-1 12 Auto-Negotiation Enable 0 = disable auto-negotiate process 1 = enable auto-negotiate process (overrides the Speed Select[0], Speed Select[1], and Duplex Mode bits of this register) R/W Note 4-1 11 Power Down 0 = normal operation 1 = General power down mode Note: Auto-Negotiation Enable must be cleared before setting this bit. R/W 0b 10 Isolate 0 = normal operation 1 = electrical isolation of PHY from RGMII R/W 0b 9 Restart Auto-Negotiate 0 = normal operation 1 = restart auto-negotiate process Note: Bit is self-clearing. R/W SC 0b 8 Duplex Mode 0 = half duplex 1 = full duplex Note: Ignored if the Auto-Negotiation Enable bit of this register is 1. R/W Note 4-1 7 RESERVED RO - 6 Speed Select[1] See description for Speed Select[0] for details. RO Note 4-1 5:0 RESERVED RO - |
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