LAN8820I datasheet(72/83 Pages) MICROCHIP

72 / 83 page

LAN8820/LAN8820I

DS00001871B-page 72

 2009-2015 Microchip Technology Inc.

5.5.5.4

PHY RXC Delay Disabled Timing

Note 5-16

7.2ns for 1000BASE-T operation, 36ns for 100BASE-TX operation, 360ns for 10BASE-T operation.

Minimum limits are non-sustainable long term.

Note 5-17

8ns for 1000BASE-T operation, 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.

Note 5-18

8.8ns for 1000BASE-T operation, 44ns for 100BASE-TX operation, 440ns for 10BASE-T operation.

Maximum limits are non-sustainable long term.

Note 5-19

45% for 1000BASE-T operation, 40% for 100BASE-TX or 10BASE-T operation.

Note 5-20

55% for 1000BASE-T operation, 60% for 100BASE-TX or 10BASE-T operation.

FIGURE 5-8:

RGMII PHY RXC DELAY DISABLED TIMING

TABLE 5-17:

RGMII PHY RXC DELAY DISABLED TIMING VALUES

Symbol

Description

Min

Typ

Max

Units

trxc

RXC period

Note 5-16

Note 5-17

Note 5-18

tclkh

RXC high time

Note 5-19

Note 5-20

tclkl

RXC low time

Note 5-19

Note 5-20

tskew

Data to clock output skew

-500

500

RXC

RXD[3:0]

RXCTRL

tclkh

tclkl

trxc

RXD

[3:0]

RXD

[7:4]

RXDV

RXER

tskew

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