LAN8820I datasheet(45/83 Pages) MICROCHIP

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DS00001871B-page 45

LAN8820/LAN8820I

4.2.14

10/100 MODE CONTROL/STATUS REGISTER

Power Optimization Disable

0 = Automatic power optimization is enabled

1 = Automatic power optimization is disabled (power consumption is

maximum)

R/W

RESERVED

LRST

Logic reset. This bit generates a reset that put all the logic into a known

state, but DOES NOT affect the register sets and 10/100 circuits. This bit is

NOT a self-clearing bit. Writing "1" to this bit generates synchronous reset.

Index (In Decimal): 17

Size:

16 bits

Bits

Description

Type

Default

EDSHORT

Energy Detect Short detection mode

0 = Normal detect mode

1 = Short detect mode

R/W

FASTRIP

10BASE-T fast mode

0 = normal operation

1 = activates PHYT_10 test mode

R/W

EDPWRDOWN

Enable the Energy Detect Power-Down mode

0 = Energy Detect Power-Down is disabled

1 = Energy Detect Power-Down is enabled

R/W

ED Power Down Mode

Select energy detect power down mode

0 = ED power down mode without NLP transmission

1 = ED power down mode with NLP transmission

R/W

11:8

RESERVED

Speed Optimize Enable

0 = Disable Speed Optimize

1 = Enable Speed Optimize

Note:

Refer to Section 3.9.5, "Speed Optimizer," on page 29 for additional

information.

R/W

AutoNeg NP Enable

0 = Next page is disabled in the auto-negotiation process

1 = Next page is enabled in the auto-negotiation process

R/W

Auto MDIX Disable

0 = Auto Xover is enabled

1 = Auto Xover is disabled selection is done manually

R/W

Bits

Description

Type

Default

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