LAN8820I datasheet(71/83 Pages) MICROCHIP

71 / 83 page

 2009-2015 Microchip Technology Inc.

DS00001871B-page 71

LAN8820/LAN8820I

5.5.5.3

PHY RXC Delay Enabled Timing

Note 5-11

7.2ns for 1000BASE-T operation, 36ns for 100BASE-TX operation, 360ns for 10BASE-T operation.

Minimum limits are non-sustainable long term.

Note 5-12

8ns for 1000BASE-T operation, 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.

Note 5-13

8.8ns for 1000BASE-T operation, 44ns for 100BASE-TX operation, 440ns for 10BASE-T operation.

Maximum limits are non-sustainable long term.

Note 5-14

45% for 1000BASE-T operation, 40% for 100BASE-TX or 10BASE-T operation.

Note 5-15

55% for 1000BASE-T operation, 60% for 100BASE-TX or 10BASE-T operation.

FIGURE 5-7:

RGMII PHY RXC DELAY ENABLED TIMING

TABLE 5-16:

RGMII PHY RXC DELAY ENABLED TIMING VALUES

Symbol

Description

Min

Typ

Max

Units

trxc

RXC period

Note 5-11

Note 5-12

Note 5-13

tclkh

RXC high time

Note 5-14

Note 5-15

tclkl

RXC low time

Note 5-14

Note 5-15

tsetup

RXD[3:0], RXCTRL output setup from edge of

RXC

1.2

thold

RXD[3:0], RXCTRL output hold from edge of

RXC

1.2

RXC

RXD[3:0]

RXCTRL

tclkh

tclkl

trxc

RXD

[3:0]

RXD

[7:4]

RXDV

RXER

thold

tsetup

thold

tsetup

thold

tsetup

thold

tsetup

LAN8820I Datasheet(PDF) 71 Page - Microchip Technology

LAN8820I Datasheet(HTML) 71 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Datasheet Download

Link URL