C501 datasheet(36/48 Pages) INFINEON

36 / 48 page

C501

Semiconductor Group

1997-04-01

AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 (cont’d)

External Data Memory Characteristics

External Clock Drive Characteristics

Parameter

Symbol

Limit Values

Unit

24 MHz

Clock

Variable Clock

CLCL = 3.5 MHz to 24 MHz

min.

max.

min.

max.

RD pulse width

RLRH

180

–

CLCL – 70

–

WR pulse width

WLWH

180

–

CLCL – 70

–

Address hold after ALE

LLAX2

–

CLCL – 27

–

RD to valid data in

RLDV

–

118

–

CLCL – 90

Data hold after RD

RHDX

–

0–ns

Data float after RD

RHDZ

–63

–

CLCL – 20

ALE to valid data in

LLDV

–

200

–

CLCL – 133

Address to valid data in

AVDV

–

220

–

CLCL – 155

ALE to WR or RD

LLWL

175

CLCL – 50

CLCL + 50

Address valid to WR or RD

AVWL

–

CLCL –

–

WR or RD high to ALE high

WHLH

CLCL – 25

CLCL + 25

Data valid to WR transition

QVWX

5–

CLCL – 37

–

Data setup before WR

QVWH

170

–

CLCL – 122

–

Data hold after WR

WHQX

–

CLCL – 27

–

Address float after RD

RLAZ

–

–0ns

Parameter

Symbol

Limit Values

Unit

Variable Clock

Freq. = 3.5 MHz to 24 MHz

min.

max.

Oscillator period

CLCL

41.7

285.7

High time

CHCX

CLCL – tCLCX

Low time

CLCX

CLCL – tCHCX

Rise time

CLCH

–12

Fall time

CHCL

–12

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