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PEF2256 Datasheet(PDF) 49 Page - Infineon Technologies AG

Part # PEF2256
Description  E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
PDF  518 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEF2256 Datasheet(HTML) 49 Page - Infineon Technologies AG

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FALC
®56
PEF 2256 H/E
Functional Description E1/T1/J1
User’s Manual
49
DS1.1, 2003-10-23
Hardware Description
3
Functional Description E1/T1/J1
3.1
Functional Overview
The FALC
®56 device contains analog and digital function blocks that are configured and
controlled by an external microprocessor or microcontroller. The functional block
diagram is shown in Figure 5.
The main interfaces are
•
Receive and transmit line interface
•
PCM system highway interface/H.100 bus
•
Microprocessor interface
•
Boundary scan interface
as well as several control lines for reset and clocking purpose.
The main internal functional blocks are
•
Analog line receiver with equalizer network and clock/data recovery
•
Analog line driver with programmable pulse shaper and line build out
•
Central clock generation module
•
Elastic buffers for receive and transmit direction
•
Receive Framer, receive line decoding, alarm detection, PRBS and performance
monitoring
•
Transmit framer, receive line encoding, alarm and PRBS generation
•
Receive jitter attenuator
•
Transmit jitter attenuator
•
Three HDLC controllers (one of them including SS7 and BOM support) and CAS
signaling controller
•
Test functions (loop switching local - remote - payload - single channel)
•
Register access interface
•
Boundary scan control



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