PEF2256 datasheet(54/518 Pages) INFINEON

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FALC

®56

PEF 2256 H/E

Functional Description E1/T1/J1

User’s Manual

DS1.1, 2003-10-23

Hardware Description

3.3.1.3

Interrupt Interface

Special events in the FALC

®56 are indicated by means of a single interrupt output with

programmable characteristics (open drain or push-pull, defined by register IPC), which

requests the CPU to read status information from the FALC

®56, or to transfer data

from/to the FALC

®56.

Since only one INT request output is provided, the cause of an interrupt must be

determined by the CPU by reading the FALC

®56’s interrupt status registers (GIS,

ISR(5:0)). The interrupt on pin INT and the interrupt status bits are reset by reading the

interrupt status registers. Register ISR(5:0) are of type “clear on read“.

The structure of the interrupt status registers is shown in Figure 8.

Figure 8

Interrupt Status Registers

Each interrupt indication of registers ISR(5:0) can be selectively masked by setting the

according bit in the corresponding mask registers IMR(5:0). If the interrupt status bits are

masked they neither generate an interrupt at INT nor are they visible in ISR(5:0).

GIS, the non-maskable Global Interrupt Status Register, serves as pointer to pending

interrupts. After the FALC

®56 has requested an interrupt by activating its INT pin, the

CPU should first read the Global Interrupt Status register GIS to identify the requesting

IMR0

F0127 V1.0

Global

Interrupt

Status

ISR0

ISR1

ISR2

ISR3

ISR4

ISR5

IMR1

ISR1

IMR2

ISR2

IMR3

ISR3

IMR4

ISR4

IMR5

ISR5

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