PEF2256 datasheet(96/518 Pages) INFINEON

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FALC

®56

PEF 2256 H/E

Functional Description E1

User’s Manual

DS1.1, 2003-10-23

Hardware Description

an external second timer is possible which has to be provided on pin SEC/FSC.

Selecting the external second timer is done with GCR.SES. Refer also to register GPC1

for input/output selection.

4.3.6

In-Band Loop Generation and Detection

The FALC

®56 generates and detects a framed or unframed in-band loop-up (activate)

and loop-down (deactivate) pattern with bit error rates up to 10

-2. Framed or unframed

in-band loop code is selected by LCR1.FLLB. Replacing transmit data with the in-band

loop codes is done by programming FMR3.XLD/XLU.

The FALC

®56 also offers the ability to generate and detect a flexible in-band loop-up and

loop-down pattern (LCR1.LLBP = 1). The loop-up and loop-down pattern is individually

programmable from 2 to 8 bits in length (LCR1.LAC1/0 and LCR1.LDC1/0).

Programming of loop codes is done in registers LCR2 and LCR3.

Status and interrupt status bits inform the user whether loop-up or loop-down code has

been detected.

4.3.7

Time Slot 0 Transparent Mode

The transparent modes are useful for loop-backs or for routing data unchanged through

the FALC

®56.

In receive direction, transparency for ternary or dual-/single-rail unipolar data is always

achieved if the receiver is in the synchronous state. In asynchronous state data is

transparently switched through if bit FMR2.DAIS is set. However, correct time slot

assignment cannot be guaranteed due to missing frame alignment between line and

system side.

Setting of bit LOOP.RTM disconnects control of the internal elastic store from the

receiver. The elastic buffer is now in a “free running” mode without any possibility to

update the time slot assignment to a new frame position in case of resynchronization of

the receiver. Together with FMR2.DAIS this function can be used to realize undisturbed

transparent reception.

Transparency in transmit direction can be achieved by activating the time slot 0

transparent mode (bit XSP.TT0 or TSWM.(7:0)). If XSP.TT0 = 1 all internal information

of the FALC

®56 (framing, CRC, S

a/Si-bit signaling, remote alarm) is ignored. With

i-bits, A-bit or the Sa-bits can be enabled selectively to send data

transparently from port XDI to the far end. For complete transparency the internal

signaling controller, idle code generation and AIS alarm generation, single channel and

payload loop-back have to be disabled.

PEF2256 Datasheet(PDF) 96 Page - Infineon Technologies AG

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