PEF2256 datasheet(10/518 Pages) INFINEON

10 / 518 page

FALC®56

PEF 2256 H/E

List of Figures

Page

User’s Manual

DS1.1, 2003-10-23

Hardware Description

Figure 1

GSM Base Station Aplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 2

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 3

Pin Configuration P-MQFP-80-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4

Pin Configuration P-LBGA-81-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 6

FIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 7

FIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 8

Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 9

Block Diagram of Test Access Port and Boundary Scan . . . . . . . . . . . 56

Figure 10

JTAG TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 11

Flexible Master Clock Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 12

Single Voltage Power Supply Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 13

Dual Voltage Power Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 14

Decoupling Capacitor Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 15

Receive Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 16

Receiver Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 17

Receive Line Monitoring (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 18

Short Haul Protection Switching Application (E1) . . . . . . . . . . . . . . . . 68

Figure 19

Long Haul Protection Switching Application (E1). . . . . . . . . . . . . . . . . 69

Figure 20

Jitter Attenuation Performance (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 21

Jitter Tolerance (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 22

The Receive Elastic Buffer as Circularly Organized Memory . . . . . . . 76

Figure 23

Automatic Handling of Errored Signaling Units . . . . . . . . . . . . . . . . . . 79

Figure 24

2.048 MHz Receive Signaling Highway (E1) . . . . . . . . . . . . . . . . . . . . 81

Figure 25

CRC4 Multiframe Alignment Recovery Algorithms (E1). . . . . . . . . . . . 92

Figure 26

Transmitter Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 27

Transmit Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 28

Transmit Line Monitor Configuration (E1) . . . . . . . . . . . . . . . . . . . . . 102

Figure 29

2.048 MHz Transmit Signaling Highway (E1) . . . . . . . . . . . . . . . . . . 104

Figure 30

System Interface (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 31

Receive System Interface Clocking (E1) . . . . . . . . . . . . . . . . . . . . . . 108

Figure 32

SYPR Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . 110

Figure 33

SYPR Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . 110

Figure 34

RFM Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . . 111

Figure 35

RFM Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . . 111

Figure 36

Transmit System Interface Clocking: 2.048 MHz (E1) . . . . . . . . . . . . 112

Figure 37

Transmit System Interface Clocking: 8.192 MHz/4.096 Mbit/s (E1). . 113

Figure 38

SYPX Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . 115

Figure 39

SYPX Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . 115

Figure 40

Remote Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 41

Payload Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 42

Local Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

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