VX6854LC datasheet(61/114 Pages) STMICROELECTRONICS

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VX6854LC

Video timing

6.2

Video timing

This section specifies the timing for the image data that is readout from the pixel array and

the output image data. These are not necessarily the same size.

The application of all of the video timing read/write parameters must be re-timed to the start

of frame boundary to ensure that the parameters are consistent within a frame.

The video stream which is output from the VX6854LC contains both video data and other

auxiliary information. The VX6854LC output coding conforms to the CCP Raw8 and Raw10

data format (see SMIA 1.0 Part 2:CCP2 Specification) including line checksums.

Reference SMIA 1.0 Specification section 5 for detailed description of video timing.

6.2.1

PLL block

The VX6854LC contains a PLL (phase locked loop) block, which generates all the

necessary internal clocks from the external clock input. Changes to the PLL settings on the

VX6854LC will only be consumed on the software standby to streaming mode transition.

Figure 21 shows the internal functional blocks, which define the relationship between the

external input clock frequency and the pixel clock frequency.

The majority of the logic within the device is clocked by vt_sys_clk however the CCI block is

clocked by the External input clock.

Figure 21. VX6854LC clock relationships

Min.

Max.

134

pll_multiplier

pre_pll_

clk_div

Range

1, 2, 4

Ext.

input

clock

External input clock

ext_clk_freq_mhz

PLL input clock

pll_ip_clk_freq_mhz

PLL output clock

pll_op_clk_freq_mhz

Video timing pixel clock

vt_pix_clk_freq_mhz

Video timing system clock

vt_sys_clk_freq_mhz

Range

1, 2

vt_sys_clk

_div

vt_pix_clk

_div

Min.

Max.

Output Timing System clock

op_sys_clk_freq_mhz

Output Timing Pixel clock

op_pix_clk_freq_mhz

op_pixel

_clk_div

op_sys_

clk_div

Min.

Max.

Range

8, 10

Max

27MHz

6MHz

Min

Max

800MHz

80MHz

38MHz

122MHz

0.757MHz

80MHz

800MHz

7.57MHz(1)

450MHz

800MHz

6MHz

12MHz

1. Note that the minimum op_sys_clk_freq_mhz is 80MHz in CSI2 mode.

VX6854LC Datasheet(PDF) 61 Page - STMicroelectronics

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