VX6854LC datasheet(23/114 Pages) STMICROELECTRONICS

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VX6854LC

Functional description

3.4.2

Power-down procedure

Table 9. Power-down sequence timing constraints for CSI2 communications

Symbol

Parameter

Min.

Max.

Units

Last I2C transaction to MIPI frame

end(1)

The whole power down sequence is triggered by the CCI power down request, however the power down

sequence will only start after the end of the frame when all active data are consumed on CSI-2 DN/DP

pins. When this is done, the CSI-2 DN/DP signals enter LP11. The CSI-2 clock will enter LP11 with a delay

of 5us (corresponding to Tclk_post + Tclk_trail) compared to DN/DP pins. The device is then

SW_STANDBY and will enter LP00 and stay in Ultra Low power mode.

1 frame

Minimum EXTCLK cycles required

after last I2C transaction or MIPI

frame end(2)

After the last frame completion, the gated clock needs to be kept for 512 cycles at least so the system can

enter Ultra Low power state. After the system enters ULPS mode, you can keep or stop the EXTCLK.

512

clock cycles

t10

Last I2C transaction or MIPI frame

end to XSHUTDOWN failling(3)

Note: XSHUTDOWN can be asserted at any time. This immediately removes the core-supply, causing the

POR to trigger and reset all the digital logic and macros - it does not depend on the presence of the clock.

When XSHUTDOWN is asserted, the clock can be running or not - it does not matter.

t8+t9

t11

XSHUTDOWN to VANA/VDIG

falling

XSHUTDOWN must fall at the

same time as, or earlier than, both

power supplies (VDIG and VANA)

t12

VANA to VDIG or VDIG to VANA

falling

VANA and VDIG may fall in any

order, the rising separation can

vary from 0 ns to indefinite

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