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VX6854LC Datasheet(PDF) 49 Page - STMicroelectronics |
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VX6854LC Datasheet(HTML) 49 Page - STMicroelectronics |
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49 / 114 page  DocID027110 Rev 2 49/114 VX6854LC Register map 69 4.26 Binning capability registers [0x1700 to 0x1719] 4.27 Data transfer capability registers [0x1800 to 0x1800] Table 37. Binning capability registers [0x1700 to 0x1719] Index Byte Register name Data type Default Type Comment 0x1700 binning_capability 8UI 01 RO VX6854LC supports binning 0x1701 binning_sub_type 8UI 02 RO VX6854LC supports two binning types 0x1702 binning_type_1 8UI 22 RO Binning type is 2x2 (col x row) 0x170B binning_weighting_capability 8UI 05 RO VX6854LC supports averaged and bayer corrected weighting 0x170C Hi min_frame_length_lines_bin 16UI 00.19 RO Minimum Frame Length allowed in binning mode. Units: Lines 0x170D Lo 0x170E Hi max_frame_length_lines_bin 16UI FF.FF RO Maximum possible number of lines per Frame allowed in binning mode. Units: Lines 0x170F Lo 0x1710 Hi min_line_length_pck_bin 16UI 09.C4 RO Minimum Line Length allowed in binning mode. Units: Pixel Clocks 0x1711 Lo 0x1712 Hi max_line_length_pck_bin 16UI 3F.FF RO Maximum possible number of pixel clocks per line. allowed in binning mode Units: Pixel Clocks 0x1713 Lo 0x1714 Hi min_line_blanking_pck_bin 16UI 05.A6 RO Minimum line blanking time in pixel clocks allowed in binning mode Units: Pixel Clocks 0x1715 Lo 0x1716 Hi fine_integration_time_min_bin 16UI 03.86 RO Minimum fine integration time. Pixel periods allowed in binning mode. Value should be 0x0197 for 2x2 0x1717 Lo 0x1718 Hi fine_integration_time_max_ margin_bin 16UI 06.3E RO Current line length – current max fine exposure allowed in binning mode. Pixel periods. Value should be 0x080F for 2x2 0x1719 Lo Table 38. Data transfer capability registers [0x1800 to 0x1800] Index Byte Register name Data type Default Type Comment 0x1800 data_xfer_if_capability 8UI 0D RO VX6854LC supports interface 1 and requires polling for both read and write. |
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