VX6854LC datasheet(76/114 Pages) STMICROELECTRONICS

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Electrical characteristics

VX6854LC

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DocID027110 Rev 2

7.7.2

CCP interface - timing characteristics

The parameters in Table 59 are measured across a terminated 100

Ω transmission line.

CCP2_signalling_mode

Figure 28. SubLVDS AC timing

For further information on the CCP refer to the specification document: SMIA 1.0 Part 2:

CCP2 Specification 30-6-04.

Table 59. CCP interface - timing characteristics

Symbol

Parameter

Min.

Max.

Unit

Average data frequency

640

Mbits/s

Average data period

1.56

Tjitter

(1)

TPmax-TPmin

Data period Jitter

200

tstable

Both data and clock at the stable level

780

Trise

Rise time of DATA+/DATA-

,CLK+/CLK-

300

400

Tfall

Fall time of DATA+/DATA-,

CLK+/CLK-

300

400

Tshew

(2)

Tshew =Tcmpshew + Tchcshew

Total skew between signals

225

tPWR

Power up/down time

μs

DATA+/

DATA-

CLK+/

CLK-

Tcmpshew

Tstable

Tchcshew

TPmin

TPmax

Tfall

Trise

80%

0.9V

20%

80%

0.9V

20%

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