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LM3554 Datasheet(PDF) 22 Page - Texas Instruments |
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LM3554 Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 47 page ![]() SCL SDA_IN SDA_OUT t 5 t 1 t 4 t 3 t 2 SDA Start Condition Stop Condition SCL S P 22 LM3554 SNVS549C – JUNE 2009 – REVISED FEBRUARY 2016 www.ti.com Product Folder Links: LM3554 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Device Functional Modes (continued) At light loads the LM3554 switches over to a pulsed frequency mode operation (light load comparator enabled). In this mode the device only switches as necessary to maintain VOUT within regulation. This mode provides a better efficiency due to the reduction in switching losses which become a larger portion of the total power loss at light loads. 7.5 Programming 7.5.1 I2C-Compatible Interface 7.5.1.1 Start and Stop Conditions The LM3554 is controlled via an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as SDA transitioning from HIGH to LOW while SCL is HIGH. A STOP condition is defined as SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates the START and STOP conditions. Figure 38. Start and Stop Sequences The I2C bus is considered busy after a START condition and free after a STOP condition. During data transmission the I2C master can generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 1 and Figure 39 show the SDA and SCL signal timing for the I2C-Compatible Bus. See Electrical Characteristics for timing values. Figure 39. I2C-Compatible Timing 7.5.1.2 I2C-Compatible Chip Address The device address for the LM3554 is 1010011 (53). After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data will be written. The third byte contains the data for the selected register. |
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