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MPD784036 Datasheet(PDF) 38 Page - NEC |
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MPD784036 Datasheet(HTML) 38 Page - NEC |
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38 / 90 page  µPD784031 38 (2) Three-wire serial I/O mode In this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. This mode is designed for communication with a device incorporating a conventional synchronous serial interface. Basically, three lines are used for communication: the serial clock line (SCK) and the two serial data lines (SI and SO). In general, a handshake line is required to check the state of communication. Figure 8-11. Block Diagram of Three-Wire Serial I/O Mode Serial clock counter SIO1, SIO2 SI1, SI2 SO1, SO2 SCK1, SCK2 fXX/2 INTCSI1, INTCSI2 Shift register Output latch Direction control circuit Internal bus Serial clock control circuit 1/m 1/2n+1 Interrupt signal generator Remark fXX: Oscillator frequency or external clock input n = 0 to 11 m = 1, 16 to 30 |
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