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LP5562 Datasheet(PDF) 25 Page - Texas Instruments

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Part # LP5562
Description  Programmable Lighting Sequences
PDF  52 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LP5562 Datasheet(HTML) 25 Page - Texas Instruments

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LP5562
www.ti.com
SNVS820A – APRIL 2013 – REVISED SEPTEMBER 2015
7.5 Programming
7.5.1 SRAM Memory
In the LP5562 there is a SRAM memory reserved for storing the LED lighting programs. Each engine has its own
section of the memory so that engine 1 has registers 10h to 2Fh, engine 2 has registers 30h to 4Fh, and engine
3 has registers 50h to 6Fh. For each engine 16 engine commands (16-bit) can be stored. Each 16-bit command
takes up two I2C registers.
Table 23. SRAM Memory Registers
Address
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Prog mem
10h
COMMAND1_ENG1[15:8]
ENG1
Prog mem
11h
COMMAND1_ENG1[7:0]
ENG1
...
Prog mem
2Eh
COMMAND16_ENG1[15:8]
ENG1
Prog mem
2Fh
COMMAND16_ENG1[7:0]
ENG1
Prog mem
30h
COMMAND1_ENG2[15:8]
ENG2
Prog mem
31h
COMMAND1_ENG2[7:0]
ENG2
...
Prog mem
4Eh
COMMAND16_ENG2[15:8]
ENG2
Prog mem
4Fh
COMMAND16_ENG2[7:0]
ENG2
Prog mem
50h
COMMAND1_ENG3[15:8]
ENG3
Prog mem
51h
COMMAND1_ENG3[7:0]
ENG3
...
Prog mem
6Eh
COMMAND16_ENG3[15:8]
ENG3
Prog mem
6Fh
COMMAND16_ENG3[7:0]
ENG3
When downloading a program to the SRAM engine modes need to be set to Load mode (see Table 6). While
loading sequential I2C writing can be used (repeated start see Figure 24). However, please note that sequential
read of the SRAM is not possible.
7.5.2 I2C-Compatible Serial Bus Interface
7.5.2.1 Interface Bus Overview
The I2C compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected
to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines
should be connected to a positive supply, via a pullup resistor and remain HIGH even when the bus is idle.
Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on
whether it generates or receives the serial clock (SCL).
Copyright © 2013–2015, Texas Instruments Incorporated
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