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LP5562 Datasheet(PDF) 36 Page - Texas Instruments |
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LP5562 Datasheet(HTML) 36 Page - Texas Instruments |
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36 / 52 page ![]() LP5562 SNVS820A – APRIL 2013 – REVISED SEPTEMBER 2015 www.ti.com 7.6.10 Engine 1 Program Counter Value Register (Engine 1 PC) (address = 09h) [reset = 00h] PC registers are synchronized to a 32-kHz clock. Delay between consecutive I2C writes to PC registers needs to be longer than 153 μs (typical). PC register can be read or written only when EXEC mode is hold. Figure 35. Engine 1 PC Value Register 7 6 5 4 3 2 1 0 ENG1_PC[3:0] R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 36. Engine 1 PC Register Field Descriptions Bit Field Type Reset Description 3:0 ENG1_PC R/W Engine 1 program counter value 7.6.11 Engine 2 Program Counter Value Register (Engine 2 PC) (address = 0Ah) [reset = 00h] PC registers are synchronized to 32-kHz clock. Delay between consecutive I2C writes to PC registers needs to be longer than 153 μs (typical). PC register can be read or written only when EXEC mode is hold. Figure 36. Engine 2 PC Value Register 7 6 5 4 3 2 1 0 ENG2_PC[3:0] R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 37. Engine 2 PC Register Field Descriptions Bit Field Type Reset Description 3:0 ENG2_PC R/W Engine 2 program counter value 7.6.12 Engine 3 Program Counter Value Register (Engine 3 PC) (address = 0Ah) [reset = 00h] PC registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to PC registers needs to be longer than 153 μs (typ.). PC register can be read or written only when EXEC mode is hold. Figure 37. Engine 3 PC Value Register 7 6 5 4 3 2 1 0 ENG3_PC[3:0] R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 38. Engine 3 PC Register Field Descriptions Bit Field Type Reset Description 3:0 ENG3_PC R/W Engine 3 program counter value 36 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LP5562 |
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