LM3533 datasheet(53/63 Pages) TI1

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LM3533

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SNOSC68C – APRIL 2012 – REVISED SEPTEMBER 2015

Layout Guidelines (continued)

2. Schottky Diode:

–

SW Pin to Schottky Anode

–

Schottky Cathode to COUT+

3. Inductor:

–

SW Node PCB capacitance to other traces

4. Input Capacitor:

–

CIN+ to IN pin

10.1.1.1 Boost Output Capacitor Selection and Placement

The LM3533 inductive boost converter requires a 1-µF output capacitor. The voltage rating of the capacitor

depends on the selected OVP setting. For the 16-V setting a 16-V capacitor must be used. For the 24-V setting a

25-V capacitor must be used. For the 32-V setting, a 35-V capacitor must be used. For the 40-V setting a 50-V

capacitor must be used. Pay careful attention to the capacitor's tolerance and DC bias response. For proper

operation the degradation in capacitance due to tolerance, DC bias, and temperature, must stay above 0.4 µF.

This might require placing two devices in parallel in order to maintain the required output capacitance over the

device operating range, and series LED configuration.

Because the output capacitor is in the path of the inductor current discharge path, a high-current step from 0 to

IPEAK is seen each time the switch turns off and the Schottky diode turns on. Any inductance along this series

path from the cathode of the diode through COUT and back into the LM3533 GND pin contributes to voltage

spikes (VSPIKE = LP_ × dI/dt) at SW and OUT. These spikes can potentially over-voltage the SW pin, or feed

through to GND. To avoid this, COUT+ must be connected as closely as possible to the cathode of the Schottky

diode, and COUT

− must be connected as closely as possible to the LM3533 device's GND pin. The best

placement for COUT is on the same layer as the LM3533 to avoid any vias that can add excessive series

inductance.

10.1.1.2 Schottky Diode Placement

The Schottky diode must have a reverse breakdown voltage greater than the LM3533 maximum output voltage

(see Overvoltage Protection (Inductive Boost)). Additionally, the diode must have an average current rating high

enough to handle the LM3533’s maximum output current, and at the same time the diode's peak current rating

must be high enough to handle the peak inductor current. Schottky diodes are required due to their lower forward

voltage drop (0.3 V to 0.5 V) and their fast recovery time.

In the LM3533 boost circuit the Schottky diode is in the path of the inductor current discharge; thus, the Schottky

diode sees a high-current step from 0 to IPEAK each time the switch turns off and the diode turns on. Any

inductance in series with the diode causes a voltage spike (VSPIKE = LP_ × dI/dt) at SW and OUT. This can

potentially over-voltage the SW pin, or feed through to VOUT and through the output capacitor and into GND.

Connecting the anode of the diode as closely as possible to the SW pin and the cathode of the diode as closely

as possible to COUT+ reduces the inductance (LP_) and minimize these voltage spikes.

10.1.1.3 Inductor Placement

The node where the inductor connects to the LM3533’s SW pin has 2 issues. First, a large switched voltage (0 to

VOUT + VF_SCHOTTKY) appears on this node every switching cycle. This switched voltage can be capacitively

coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces connecting the

input supply to the inductor and connecting the inductor to the SW pin. Any resistance in this path can cause

voltage drops that can negatively affect efficiency and reduce the input operating voltage range.

To reduce the capacitive coupling of the signal on SW into nearby traces, the SW pin-to-inductor connection

must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, high-

impedance nodes that are more susceptible to electric field coupling need to be routed away from SW and not

directly adjacent or beneath. This is especially true for traces such as SCL, SDA, HWEN, PWM, and possibly

ALS. A GND plane placed directly below SW dramatically reduces the capacitance from SW into nearby traces.

Lastly, limit the trace resistance of the VBATT-to-inductor connection and from the inductor-to-SW connection, by

use of short, wide traces.

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