TSC2102IDA datasheet(42/54 Pages) TI

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TSC2102

SLAS379A− APRIL 2003 − REVISED JUNE 2004

www.ti.com

BIT

NAME

READ/

WRITE

RESET VALUE

FUNCTION

D15

Reserved

Reserved. Write only 0 to this location.

D14

DASTPD

R/W

DAC Soft-Stepping Control

0 => Soft-stepping is enabled

1 => Soft-stepping is disabled

D13−D2

Reserved

000000000000

Reserved. Write only 000000000000 in this location.

D1−D0

Reserved

Reserved (write only 00)

LAYOUT

The following layout suggestions should provide optimum performance from the TSC2102. However, many portable

applications have conflicting requirements concerning power, cost, size, and weight. In general, most portable devices

have fairly clean power and grounds because most of the internal components are very low power. This situation means

less bypassing for the converter power and less concern regarding grounding. Still, each situation is unique and the

following suggestions should be reviewed carefully.

For optimum performance, care must be taken with the physical layout of the TSC2102 circuitry. The basic SAR architecture

is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur

just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter,

there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches might

originate from switching power supplies, nearby digital logic, and high power devices. The degree of error in the digital

output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the

external event changes in time with respect to the timing of the critical n windows.

With this in mind, power to the TSC2102 must be clean and well bypassed. A 0.1-

µF ceramic bypass capacitor must be

placed as close to the device as possible. A 1-

µF to 10-µF capacitor may also be needed if the impedance between the

TSC2102 supply pins and the system power supply is high.

The VREF pin requires a minimum bypass capacitor of 0.1

µF, although a larger value can be used to reduce the reference

noise level. If an external reference voltage originates from an op-amp, make sure that it can drive any bypass capacitor

that is used without oscillation.

The TSC2102 architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference

input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply

appears directly in the digital results. While high frequency noise can be filtered out, voltage variation due to line frequency

(50 Hz or 60 Hz) can be difficult to remove.

The ground pins must be connected to a clean ground point. In many cases, this is the analog ground. Avoid connections

that are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly

from the converter to the power supply entry or battery connection point. The ideal layout includes an analog ground plane

dedicated to the converter and associated analog circuitry.

In the specific case of use with a resistive touch screen, care must be taken with the connection between the converter

and the touch screen. Since resistive touch screens have fairly low resistance, the interconnection must be as short and

robust as possible. Loose connections can be a source of error when the contact resistance changes with flexing or

vibrations.

As indicated previously, noise can be a major source of error in touch-screen applications (e.g., applications that require

a back-lit LCD panel). This EMI noise can be coupled through the LCD panel to the touch screen and cause flickering of

the converted ADC data. Several things can be done to reduce this error, such as utilizing a touch screen with a bottom-side

metal layer connected to ground. This couples the majority of noise to ground. Additionally, filtering capacitors, from Y+,

Y–, X+, and X– to ground, can also help. Note, however, that the use of these capacitors increases screen settling time

and requires longer panel voltage stabilization times, as well as increased precharge and sense times for the PINTDAV

circuitry of the TSC2102.

TSC2102IDA Datasheet(PDF) 42 Page - Texas Instruments

TSC2102IDA Datasheet(HTML) 42 Page - Texas Instruments

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