TSC2102IDA datasheet(52/54 Pages) TI

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TSC2102

SLAS379A− APRIL 2003 − REVISED JUNE 2004

www.ti.com

De-Emphasis Error at 48 ksps

PLL PROGRAMMING

The on-chip PLL in the TSC2102 can be used to generate sampling clocks from a wide range of MCLK’s available in a

system. The PLL works by generating oversampled clocks with respect to Fsref (44.1 kHz or 48 kHz). Frequency division

generates all other internal clocks. The table below gives a sample programming for PLL registers for some standard

MCLKs when PLL is required. Whenever the MCLK is of the form of N*128*Fsref (N=2,3

…), PLL is not required.

Fsref = 44.1 kHz

MCLK (MHz)

ACHIEVED FSREF

% ERROR

2.8224

44100.00

0.0000

5.6448

44100.00

0.0000

5264

44100.00

0.0000

9474

44099.71

0.0007

6448

44100.00

0.0000

19.2

7040

44100.00

0.0000

19.68

5893

44100.30

−0.0007

5264

44100.00

0.0000

Fsref = 48 kHz

MCLK (MHz)

ACHIEVED FSREF

% ERROR

2.048

48000.00

0.0000

3.072

48000.00

0.0000

4.096

48000.00

0.0000

6.144

48000.00

0.0000

8.192

48000.00

0.0000

1920

48000.00

0.0000

5618

47999.71

0.0006

1440

48000.00

0.0000

19.2

1200

48000.00

0.0000

19.68

9951

47999.79

0.0004

1920

48000.00

0.0000

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