TSC2102IDA datasheet(28/54 Pages) TI

28 / 54 page

TSC2102

SLAS379A− APRIL 2003 − REVISED JUNE 2004

www.ti.com

Table 2. Page Addressing

PG3

PG2

PG1

PG0

PAGE ADDRESSED

Reserved

To read all the first page of memory, for example, the host processor must send the TSC2102 the command 0x8000 – this

specifies a read operation beginning at page 0, address 0. The processor can then start clocking data out of the TSC2102.

The TSC2102 automatically increments its address pointer to the end of the page; if the host processor continues clocking

data out past the end of a page, the TSC2102 sends back the value 0xFFFF.

Likewise, writing to page 1 of memory consists of the processor writing the command 0x0800, which specifies a write

operation, with PG0 set to 1, and all the ADDR bits set to 0. This results in the address pointer pointing at the first location

in memory on Page 1. See the section on the TSC2102 memory map for details of register locations

BIT 15

MSB

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

LSB

R/W*

PG3

PG2

PG1

PG0

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

Figure 23. TSC2102 Command Word

COMMAND WORD

DATA

SCLK

MOSI

Figure 24. Write Operation for TSC2102 SPI Interface

TSC2102IDA Datasheet(PDF) 28 Page - Texas Instruments

TSC2102IDA Datasheet(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Datasheet Download

Link URL