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DP83266 Datasheet(PDF) 109 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 109 Page - National Semiconductor (TI) |
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109 / 152 page  70 Control Information (Continued) Indicate Notify Register (INR) The Indicate Notify Register (INR) is used to enable attentions in the Indicate Attention Register (IAR) If a bit in Register INR is set to One the corresponding bit in Register IAR will be applied to the Master Attention Register which can be used to generate an interrupt to the host All bits in this register are set to Zero upon reset Access Rules Address Read Write 115h Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 RES RES EXC0N BRK0N EXC1N BRK1N EXC2N BRK2N Bit Symbol Description D0 BRK2N Breakpoint on ICHN2 Notify This bit is used to enable the BRK2 bit in Register IAR D1 EXC2N Exception on ICHN2 Notify This bit is used to enable the EXC2 bit in Register IAR D2 BRK1N Breakpoint on ICHN1 Notify This bit is used to enable the BRK1 bit in Register IAR D3 EXC1N Exception on ICHN1 Notify This bit is used to enable the EXC1 bit in Register IAR D4 BRK0N Breakpoint on ICHN0 Notify This bit is used to enable the BRK0 bit in Register IAR D5 EXC0N Exception on ICHN0 Notify This bit is used to enable the EXC0 bit in Register IAR D7 – D6 RES Reserved Indicate Threshold Register (ITR) The Indicate Threshold Register (ITR) specifies the maximum number of frames that can be received on Indicate Channel 1 or Indicate Channel 2 before an attention will be generated This register may be written only when the INSTOP bit in the State Attention Register is set or when the Indicate Channel’s corresponding EXC bit in the Indicate Attention Register is set This register is not altered upon reset Access Rules Address Read Write 116h Always INSTOP Mode or EXC e 1 Only Register Bits D7 D6 D5 D4 D3 D2 D1 D0 THR7 THR6 THR5 THR4 THR3 THR2 THR1 THR0 Bit Symbol Description D7–D0 THR7–0 Threshold Data Bits 7 – 0 The value programmed in this register is loaded into an internal counter every time the Indicate Channel changes Each valid frame copied on the current Channel decrements the counter When the counter reaches Zero a status breakpoint attention is generated (ie the Channel’s BRK bit in the Indicate Attention Register is set) if the Channel’s Breakpoint on Threshold (BOT) bit in the Indicate Mode Register is set Loading the Indicate Threshold Register with Zero generates a breakpoint after 256 consecutive frames are received on any one Indicate Channel 109 |
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